Updated MFMM (markdown)

Sun Yimin 2021-12-20 08:44:11 +08:00
parent 7d1219c4d5
commit ec0cbbad90

@ -63,7 +63,7 @@ acc0, acc1, acc2, acc3, acc4, acc5是64位寄存器
UMULH acc0, const1, acc0 // acc0 = H(acc0 * p3) UMULH acc0, const1, acc0 // acc0 = H(acc0 * p3)
ADCS t0, acc2 // (carry2, acc2) = carry1 + acc2 + H(acc0 * 2^32) ADCS t0, acc2 // (carry2, acc2) = carry1 + acc2 + H(acc0 * 2^32)
ADCS t1, acc3 // (carry3, acc3) = carry2 + acc3 + L(acc0 * p3) ADCS t1, acc3 // (carry3, acc3) = carry2 + acc3 + L(acc0 * p3)
ADC $0, acc0 // acc0 = carry3 + H(acc0 * p3), why? 猜测后续有优化 ADC $0, acc0 // acc0 = carry3 + H(acc0 * p3), arm64的实现((acc0, acc4), acc3, acc2, acc1)表示第一次reduction的结果, 不像amd64那样使用acc5, acc4, acc3, acc2, acc1
SM2曲线 SM2曲线
p = 0x fffffffeffffffff ffffffffffffffff ffffffff00000000 ffffffffffffffff p = 0x fffffffeffffffff ffffffffffffffff ffffffff00000000 ffffffffffffffff