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Updated SM3性能优化 (markdown)

Sun Yimin 2023-09-19 09:53:41 +08:00
parent 12b312a4af
commit a053077a53
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SM3性能优化.md

@ -237,6 +237,58 @@ SM3的第一版，比SHA256复杂，不知道有没有继续优化的空间。
VPXOR XTMP1, XTMP0, XDWORD0; \ // XTMP1 = {W[3], W[2], W[1], W[0]}
```
第四版（优化第一次P1实现）：
```asm
// Wj ← P1(Wj−16 ⊕ Wj−9 ⊕ (Wj−3 ≪ 15)) ⊕ (Wj−13 ≪ 7) ⊕ Wj−6
// Transpose data into high/low parts
VPERM2I128 $0x20, XTMP2, XTMP0, XDWORD0 // w3, w2, w1, w0
VPERM2I128 $0x31, XTMP2, XTMP0, XDWORD1 // w7, w6, w5, w4
VPERM2I128 $0x20, XTMP3, XTMP1, XDWORD2 // w11, w10, w9, w8
VPERM2I128 $0x31, XTMP3, XTMP1, XDWORD3 // w15, w14, w13, w12
VPALIGNR $12, XDWORD0, XDWORD1, XTMP0; \ // XTMP0 = W[-13] = {w6,w5,w4,w3}
VPSLLD $7, XTMP0, XTMP1; \
VPSRLD $(32-7), XTMP0, XTMP0; \
VPOR XTMP0, XTMP1, XTMP1; \ // XTMP1 = W[-13] rol 7
VPALIGNR $8, XDWORD2, XDWORD3, XTMP0; \ // XTMP0 = W[-6] = {w13,w12,w11,w10}
VPXOR XTMP1, XTMP0, XTMP0; \ // XTMP0 = W[-6] XOR (W[-13] rol 7)
// Prepare P1 parameters
VPALIGNR $12, XDWORD1, XDWORD2, XTMP1; \ // XTMP1 = W[-9] = {w10,w9,w8,w7}
VPXOR XDWORD0, XTMP1, XTMP1; \ // XTMP1 = W[-9] XOR W[-16]
VPSHUFD $0xA5, XDWORD3, XTMP2; \ // XTMP2 = W[-3] {BBAA} {w14,w14,w13,w13}
VPSRLQ $17, XTMP2, XTMP2; \ // XTMP2 = W[-3] ror 17 {xBxA}
VPXOR XTMP1, XTMP2, XTMP2; \ // XTMP2 = W[-9] XOR W[-16] XOR (W[-3] rol 15) {xxxA}
// P1
VPSHUFD $0x55, XTMP2, XTMP2; \ // XTMP2 = W[-9] XOR W[-16] XOR (W[-3] rol 15) {xxAA}
VPSRLQ $17, XTMP2, XTMP3; \ // XTMP3 = XTMP2 rol 15 {xxxA}
VPSRLQ $9, XTMP2, XTMP4; \ // XTMP4 = XTMP2 rol 9 {xxxA}
VPXOR XTMP2, XTMP4, XTMP4; \ // XTMP4 = XTMP2 XOR (XTMP2 rol 15 {xxxA})
VPXOR XTMP4, XTMP3, XTMP4; \ // XTMP4 = XTMP2 XOR (XTMP2 rol 15 {xxxA}) XOR (XTMP2 rol 23 {xxxA})
// First 1 words message schedule result
VPXOR XTMP4, XTMP0, XTMP2; \ // XTMP2 = {..., ..., ..., W[0]}
// Prepare P1 parameters
VPALIGNR $4, XDWORD3, XTMP2, XTMP3; \ // XTMP3 = {W[0], w15, w14, w13}
VPSLLD $15, XTMP3, XTMP4; \
VPSRLD $(32-15), XTMP4, XTMP4; \
VPOR XTMP3, XTMP4, XTMP4; \ // XTMP4 = W[-3] rol 15 {DCBA}
VPXOR XTMP1, XTMP4, XTMP4; \ // XTMP4 = W[-9] XOR W[-16] XOR (W[-3] rol 15) {DCBA}
// P1
VPSLLD $15, XTMP4, XTMP5; \
VPSRLD $(32-15), XTMP4, XTMP3; \
VPOR XTMP3, XTMP5, XTMP3; \ // XTMP3 = XTMP4 rol 15 {DCBA}
VPSHUFB r08_mask<>(SB), XTMP3, XTMP1; \ // XTMP1 = XTMP4 rol 23 {DCBA}
VPXOR XTMP3, XTMP4, XTMP3; \ // XTMP3 = XTMP4 XOR (XTMP4 rol 15 {DCBA})
VPXOR XTMP3, XTMP1, XTMP1; \ // XTMP1 = XTMP4 XOR (XTMP4 rol 15 {DCBA}) XOR (XTMP4 rol 23 {DCBA})
// 4 words message schedule result
VPXOR XTMP1, XTMP0, XDWORD0; \ // XTMP1 = {W[3], W[2], W[1], W[0]}
```
ARM64 NEON 版（没有用VTBL表查询指令）：
```asm
VEXT $12, XWORD1.B16, XWORD0.B16, XTMP0.B16; // XTMP0 = W[-13] = {w6,w5,w4,w3}, Vm = XWORD1, Vn = XWORD0