mirror of
https://github.com/emmansun/gmsm.git
synced 2025-04-25 19:56:18 +08:00
750 lines
38 KiB
ArmAsm
750 lines
38 KiB
ArmAsm
// shuffle byte order from LE to BE
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DATA flip_mask<>+0x00(SB)/8, $0x0405060700010203
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DATA flip_mask<>+0x08(SB)/8, $0x0c0d0e0f08090a0b
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GLOBL flip_mask<>(SB), 8, $16
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// shuffle byte and word order
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DATA bswap_mask<>+0x00(SB)/8, $0x08090a0b0c0d0e0f
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DATA bswap_mask<>+0x08(SB)/8, $0x0001020304050607
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GLOBL bswap_mask<>(SB), 8, $16
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//nibble mask
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DATA nibble_mask<>+0x00(SB)/8, $0x0F0F0F0F0F0F0F0F
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DATA nibble_mask<>+0x08(SB)/8, $0x0F0F0F0F0F0F0F0F
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GLOBL nibble_mask<>(SB), 8, $16
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// inverse shift rows
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DATA inverse_shift_rows<>+0x00(SB)/8, $0x0B0E0104070A0D00
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DATA inverse_shift_rows<>+0x08(SB)/8, $0x0306090C0F020508
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GLOBL inverse_shift_rows<>(SB), 8, $16
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// Affine transform 1 (low and high hibbles)
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DATA m1_low<>+0x00(SB)/8, $0x0A7FC3B6D5A01C69
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DATA m1_low<>+0x08(SB)/8, $0x3045F98CEF9A2653
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GLOBL m1_low<>(SB), 8, $16
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DATA m1_high<>+0x00(SB)/8, $0xC35BF46CAF379800
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DATA m1_high<>+0x08(SB)/8, $0x68F05FC7049C33AB
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GLOBL m1_high<>(SB), 8, $16
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// Affine transform 2 (low and high hibbles)
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DATA m2_low<>+0x00(SB)/8, $0x9A950A05FEF16E61
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DATA m2_low<>+0x08(SB)/8, $0x0E019E916A65FAF5
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GLOBL m2_low<>(SB), 8, $16
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DATA m2_high<>+0x00(SB)/8, $0x892D69CD44E0A400
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DATA m2_high<>+0x08(SB)/8, $0x2C88CC68E14501A5
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GLOBL m2_high<>(SB), 8, $16
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// left rotations of 32-bit words by 8-bit increments
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DATA r08_mask<>+0x00(SB)/8, $0x0605040702010003
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DATA r08_mask<>+0x08(SB)/8, $0x0E0D0C0F0A09080B
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GLOBL r08_mask<>(SB), 8, $16
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DATA r16_mask<>+0x00(SB)/8, $0x0504070601000302
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DATA r16_mask<>+0x08(SB)/8, $0x0D0C0F0E09080B0A
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GLOBL r16_mask<>(SB), 8, $16
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DATA r24_mask<>+0x00(SB)/8, $0x0407060500030201
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DATA r24_mask<>+0x08(SB)/8, $0x0C0F0E0D080B0A09
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GLOBL r24_mask<>(SB), 8, $16
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DATA fk_mask<>+0x00(SB)/8, $0x56aa3350a3b1bac6
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DATA fk_mask<>+0x08(SB)/8, $0xb27022dc677d9197
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GLOBL fk_mask<>(SB), 8, $16
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// inverse shift rows
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DATA inverse_shift_rows256<>+0x00(SB)/8, $0x0B0E0104070A0D00
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DATA inverse_shift_rows256<>+0x08(SB)/8, $0x0306090C0F020508
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DATA inverse_shift_rows256<>+0x10(SB)/8, $0x0B0E0104070A0D00
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DATA inverse_shift_rows256<>+0x18(SB)/8, $0x0306090C0F020508
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GLOBL inverse_shift_rows256<>(SB), 8, $32
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DATA r08_mask256<>+0x00(SB)/8, $0x0605040702010003
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DATA r08_mask256<>+0x08(SB)/8, $0x0E0D0C0F0A09080B
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DATA r08_mask256<>+0x10(SB)/8, $0x0605040702010003
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DATA r08_mask256<>+0x18(SB)/8, $0x0E0D0C0F0A09080B
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GLOBL r08_mask256<>(SB), 8, $32
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DATA r16_mask256<>+0x00(SB)/8, $0x0504070601000302
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DATA r16_mask256<>+0x08(SB)/8, $0x0D0C0F0E09080B0A
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DATA r16_mask256<>+0x10(SB)/8, $0x0504070601000302
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DATA r16_mask256<>+0x18(SB)/8, $0x0D0C0F0E09080B0A
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GLOBL r16_mask256<>(SB), 8, $32
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DATA r24_mask256<>+0x00(SB)/8, $0x0407060500030201
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DATA r24_mask256<>+0x08(SB)/8, $0x0C0F0E0D080B0A09
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DATA r24_mask256<>+0x10(SB)/8, $0x0407060500030201
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DATA r24_mask256<>+0x18(SB)/8, $0x0C0F0E0D080B0A09
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GLOBL r24_mask256<>(SB), 8, $32
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// Transpose matrix without PUNPCKHDQ/PUNPCKLDQ/PUNPCKHQDQ/PUNPCKLQDQ instructions, bad performance!
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// input: from high to low
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// r0 = [w3, w2, w1, w0]
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// r1 = [w7, w6, w5, w4]
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// r2 = [w11, w10, w9, w8]
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// r3 = [w15, w14, w13, w12]
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// r: 32/64 temp register
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// tmp1: 128 bits temp register
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// tmp2: 128 bits temp register
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//
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// output: from high to low
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// r0 = [w12, w8, w4, w0]
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// r1 = [w13, w9, w5, w1]
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// r2 = [w14, w10, w6, w2]
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// r3 = [w15, w11, w7, w3]
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//
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// SSE2/MMX instructions:
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// MOVOU r0, tmp2;
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// PUNPCKHDQ r1, tmp2;
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// PUNPCKLDQ r1, r0;
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// MOVOU r2, tmp1;
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// PUNPCKLDQ r3, tmp1;
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// PUNPCKHDQ r3, r2;
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// MOVOU r0, r1;
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// PUNPCKHQDQ tmp1, r1;
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// PUNPCKLQDQ tmp1, r0;
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// MOVOU tmp2, r3;
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// PUNPCKHQDQ r2, r3;
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// PUNPCKLQDQ r2, tmp2;
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// MOVOU tmp2, r2
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#define SSE_TRANSPOSE_MATRIX(r0, r1, r2, r3, tmp1, tmp2) \
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MOVOU r0, tmp2; \
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PUNPCKHLQ r1, tmp2; \
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PUNPCKLLQ r1, r0; \
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MOVOU r2, tmp1; \
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PUNPCKLLQ r3, tmp1; \
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PUNPCKHLQ r3, r2; \
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MOVOU r0, r1; \
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PUNPCKHQDQ tmp1, r1; \
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PUNPCKLQDQ tmp1, r0; \
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MOVOU tmp2, r3; \
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PUNPCKHQDQ r2, r3; \
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PUNPCKLQDQ r2, tmp2; \
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MOVOU tmp2, r2
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// SM4 sbox function
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// parameters:
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// - x: 128 bits register as sbox input/output data
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// - y: 128 bits temp register
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// - z: 128 bits temp register
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#define SM4_SBOX(x, y, z) \
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; \ //############################# inner affine ############################//
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MOVOU x, z; \
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PAND nibble_mask<>(SB), z; \ //y = _mm_and_si128(x, c0f);
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MOVOU m1_low<>(SB), y; \
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PSHUFB z, y; \ //y = _mm_shuffle_epi8(m1l, y);
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PSRLQ $4, x; \ //x = _mm_srli_epi64(x, 4);
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PAND nibble_mask<>(SB), x; \ //x = _mm_and_si128(x, c0f);
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MOVOU m1_high<>(SB), z; \
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PSHUFB x, z; \ //x = _mm_shuffle_epi8(m1h, x);
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MOVOU z, x; \ //x = _mm_shuffle_epi8(m1h, x);
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PXOR y, x; \ //x = _mm_shuffle_epi8(m1h, x) ^ y;
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; \ // inverse ShiftRows
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PSHUFB inverse_shift_rows<>(SB), x; \ //x = _mm_shuffle_epi8(x, shr);
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AESENCLAST nibble_mask<>(SB), x; \ // AESNI instruction
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; \ //############################# outer affine ############################//
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MOVOU x, z; \
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PANDN nibble_mask<>(SB), z; \ //z = _mm_andnot_si128(x, c0f);
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MOVOU m2_low<>(SB), y; \
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PSHUFB z, y; \ //y = _mm_shuffle_epi8(m2l, z)
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PSRLQ $4, x; \ //x = _mm_srli_epi64(x, 4);
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PAND nibble_mask<>(SB), x; \ //x = _mm_and_si128(x, c0f);
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MOVOU m2_high<>(SB), z; \
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PSHUFB x, z; \
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MOVOU z, x; \ //x = _mm_shuffle_epi8(m2h, x)
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PXOR y, x //x = _mm_shuffle_epi8(m2h, x) ^ y;
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// SM4 TAO L1 function
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// parameters:
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// - x: 128 bits register as TAO_L1 input/output data
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// - y: 128 bits temp register
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// - z: 128 bits temp register
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#define SM4_TAO_L1(x, y, z) \
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SM4_SBOX(x, y, z); \
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; \ //#################### 4 parallel L1 linear transforms ##################//
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MOVOU x, y; \
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PSHUFB r08_mask<>(SB), y; \ //y = _mm_shuffle_epi8(x, r08)
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PXOR x, y; \ //y = x xor _mm_shuffle_epi8(x, r08)
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MOVOU x, z; \
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PSHUFB r16_mask<>(SB), z; \
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PXOR z, y; \ //y = x xor _mm_shuffle_epi8(x, r08) xor _mm_shuffle_epi8(x, r16)
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MOVOU y, z; \
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PSLLL $2, z; \
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PSRLL $30, y; \
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POR z, y; \ //y = _mm_slli_epi32(y, 2) ^ _mm_srli_epi32(y, 30);
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MOVOU x, z; \
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PSHUFB r24_mask<>(SB), z; \
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PXOR y, x; \ //x = x xor y
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PXOR z, x //x = x xor y xor _mm_shuffle_epi8(x, r24);
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// SM4 single round function, handle 16 bytes data
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// t0 ^= tao_l1(t1^t2^t3^xk)
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// used R19 as temp 32/64 bits register
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// parameters:
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// - index: round key index immediate number
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// - RK: round key register
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// - IND: round key index base register
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// - x: 128 bits temp register
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// - y: 128 bits temp register
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// - z: 128 bits temp register
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// - t0: 128 bits register for data as result
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// - t1: 128 bits register for data
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// - t2: 128 bits register for data
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// - t3: 128 bits register for data
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#define SM4_SINGLE_ROUND(index, RK, IND, x, y, z, t0, t1, t2, t3) \
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MOVL (index * 4)(RK)(IND*1), x; \
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PXOR t1, x; \
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PXOR t2, x; \
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PXOR t3, x; \
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SM4_TAO_L1(x, y, z); \
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PXOR x, t0
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// SM4 round function, handle 64 bytes data
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// t0 ^= tao_l1(t1^t2^t3^xk)
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// parameters:
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// - index: round key index immediate number
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// - RK: round key register
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// - IND: round key index base register
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// - x: 128 bits temp register
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// - y: 128 bits temp register
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// - z: 128 bits temp register
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// - t0: 128 bits register for data as result
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// - t1: 128 bits register for data
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// - t2: 128 bits register for data
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// - t3: 128 bits register for data
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#define SM4_ROUND(index, RK, IND, x, y, z, t0, t1, t2, t3) \
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MOVL (index * 4)(RK)(IND*1), x; \
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PSHUFD $0, x, x; \
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PXOR t1, x; \
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PXOR t2, x; \
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PXOR t3, x; \
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SM4_TAO_L1(x, y, z); \
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PXOR x, t0
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#define SM4_ONE_ROUND_SSE(x, y, z, t0, t1, t2, t3) \
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PXOR t1, x; \
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PXOR t2, x; \
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PXOR t3, x; \
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SM4_TAO_L1(x, y, z); \
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PXOR x, t0 \
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#define SM4_4BLOCKS_4ROUNDS(rk128, x, y, z, t0, t1, t2, t3) \
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PSHUFD $0, rk128, x; \
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SM4_ONE_ROUND_SSE(x, y, z, t0, t1, t2, t3); \
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PSHUFD $0x55, rk128, x; \
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SM4_ONE_ROUND_SSE(x, y, z, t1, t2, t3, t0); \
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PSHUFD $0xAA, rk128, x; \
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SM4_ONE_ROUND_SSE(x, y, z, t2, t3, t0, t1); \
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PSHUFD $0xFF, rk128, x; \
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SM4_ONE_ROUND_SSE(x, y, z, t3, t0, t1, t2); \
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#define SM4_SINGLE_BLOCK(RK, rk128, x, y, z, t0, t1, t2, t3) \
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PSHUFB flip_mask<>(SB), t0; \
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PSHUFD $1, t0, t1; \
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PSHUFD $2, t0, t2; \
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PSHUFD $3, t0, t3; \
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MOVOU (0*16)(RK), rk128; \
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SM4_4BLOCKS_4ROUNDS(rk128, x, y, z, t0, t1, t2, t3); \
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MOVOU (1*16)(RK), rk128; \
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SM4_4BLOCKS_4ROUNDS(rk128, x, y, z, t0, t1, t2, t3); \
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MOVOU (2*16)(RK), rk128; \
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SM4_4BLOCKS_4ROUNDS(rk128, x, y, z, t0, t1, t2, t3); \
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MOVOU (3*16)(RK), rk128; \
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SM4_4BLOCKS_4ROUNDS(rk128, x, y, z, t0, t1, t2, t3); \
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MOVOU (4*16)(RK), rk128; \
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SM4_4BLOCKS_4ROUNDS(rk128, x, y, z, t0, t1, t2, t3); \
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MOVOU (5*16)(RK), rk128; \
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SM4_4BLOCKS_4ROUNDS(rk128, x, y, z, t0, t1, t2, t3); \
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MOVOU (6*16)(RK), rk128; \
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SM4_4BLOCKS_4ROUNDS(rk128, x, y, z, t0, t1, t2, t3); \
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MOVOU (7*16)(RK), rk128; \
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SM4_4BLOCKS_4ROUNDS(rk128, x, y, z, t0, t1, t2, t3); \
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PALIGNR $4, t3, t3; \
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PALIGNR $4, t3, t2; \
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PALIGNR $4, t2, t1; \
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PALIGNR $4, t1, t0; \
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PSHUFB flip_mask<>(SB), t0
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#define SM4_4BLOCKS(RK, rk128, x, y, z, t0, t1, t2, t3) \
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PSHUFB flip_mask<>(SB), t0; \
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PSHUFB flip_mask<>(SB), t1; \
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PSHUFB flip_mask<>(SB), t2; \
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PSHUFB flip_mask<>(SB), t3; \
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SM4_4BLOCKS_WO_BS(RK, rk128, x, y, z, t0, t1, t2, t3)
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#define SM4_4BLOCKS_WO_BS(RK, rk128, x, y, z, t0, t1, t2, t3) \
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SSE_TRANSPOSE_MATRIX(t0, t1, t2, t3, x, y); \
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MOVOU (0*16)(RK), rk128; \
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SM4_4BLOCKS_4ROUNDS(rk128, x, y, z, t0, t1, t2, t3); \
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MOVOU (1*16)(RK), rk128; \
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SM4_4BLOCKS_4ROUNDS(rk128, x, y, z, t0, t1, t2, t3); \
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MOVOU (2*16)(RK), rk128; \
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SM4_4BLOCKS_4ROUNDS(rk128, x, y, z, t0, t1, t2, t3); \
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MOVOU (3*16)(RK), rk128; \
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SM4_4BLOCKS_4ROUNDS(rk128, x, y, z, t0, t1, t2, t3); \
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MOVOU (4*16)(RK), rk128; \
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SM4_4BLOCKS_4ROUNDS(rk128, x, y, z, t0, t1, t2, t3); \
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MOVOU (5*16)(RK), rk128; \
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SM4_4BLOCKS_4ROUNDS(rk128, x, y, z, t0, t1, t2, t3); \
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MOVOU (6*16)(RK), rk128; \
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SM4_4BLOCKS_4ROUNDS(rk128, x, y, z, t0, t1, t2, t3); \
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MOVOU (7*16)(RK), rk128; \
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SM4_4BLOCKS_4ROUNDS(rk128, x, y, z, t0, t1, t2, t3); \
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SSE_TRANSPOSE_MATRIX(t0, t1, t2, t3, x, y); \
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PSHUFB bswap_mask<>(SB), t3; \
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PSHUFB bswap_mask<>(SB), t2; \
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PSHUFB bswap_mask<>(SB), t1; \
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PSHUFB bswap_mask<>(SB), t0
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#define SM4_8BLOCKS_4ROUNDS(rk128, x, y, z, t0, t1, t2, t3, t4, t5, t6, t7) \
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PSHUFD $0, rk128, x; \
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SM4_ONE_ROUND_SSE(x, y, z, t0, t1, t2, t3); \
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PSHUFD $0, rk128, x; \
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SM4_ONE_ROUND_SSE(x, y, z, t4, t5, t6, t7); \
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PSHUFD $0x55, rk128, x; \
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SM4_ONE_ROUND_SSE(x, y, z, t1, t2, t3, t0); \
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PSHUFD $0x55, rk128, x; \
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SM4_ONE_ROUND_SSE(x, y, z, t5, t6, t7, t4); \
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PSHUFD $0xAA, rk128, x; \
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SM4_ONE_ROUND_SSE(x, y, z, t2, t3, t0, t1); \
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PSHUFD $0xAA, rk128, x; \
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SM4_ONE_ROUND_SSE(x, y, z, t6, t7, t4, t5); \
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PSHUFD $0xFF, rk128, x; \
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SM4_ONE_ROUND_SSE(x, y, z, t3, t0, t1, t2); \
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PSHUFD $0xFF, rk128, x; \
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SM4_ONE_ROUND_SSE(x, y, z, t7, t4, t5, t6); \
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#define SM4_8BLOCKS(RK, rk128, x, y, z, t0, t1, t2, t3, t4, t5, t6, t7) \
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PSHUFB flip_mask<>(SB), t0; \
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PSHUFB flip_mask<>(SB), t1; \
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PSHUFB flip_mask<>(SB), t2; \
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PSHUFB flip_mask<>(SB), t3; \
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PSHUFB flip_mask<>(SB), t4; \
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PSHUFB flip_mask<>(SB), t5; \
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PSHUFB flip_mask<>(SB), t6; \
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PSHUFB flip_mask<>(SB), t7; \
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SM4_8BLOCKS_WO_BS(RK, rk128, x, y, z, t0, t1, t2, t3, t4, t5, t6, t7)
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#define SM4_8BLOCKS_WO_BS(RK, rk128, x, y, z, t0, t1, t2, t3, t4, t5, t6, t7) \
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SSE_TRANSPOSE_MATRIX(t0, t1, t2, t3, x, y); \
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SSE_TRANSPOSE_MATRIX(t4, t5, t6, t7, x, y); \
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MOVOU (0*16)(RK), rk128; \
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SM4_8BLOCKS_4ROUNDS(rk128, x, y, z, t0, t1, t2, t3, t4, t5, t6, t7); \
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MOVOU (1*16)(RK), rk128; \
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SM4_8BLOCKS_4ROUNDS(rk128, x, y, z, t0, t1, t2, t3, t4, t5, t6, t7); \
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MOVOU (2*16)(RK), rk128; \
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SM4_8BLOCKS_4ROUNDS(rk128, x, y, z, t0, t1, t2, t3, t4, t5, t6, t7); \
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MOVOU (3*16)(RK), rk128; \
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SM4_8BLOCKS_4ROUNDS(rk128, x, y, z, t0, t1, t2, t3, t4, t5, t6, t7); \
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MOVOU (4*16)(RK), rk128; \
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SM4_8BLOCKS_4ROUNDS(rk128, x, y, z, t0, t1, t2, t3, t4, t5, t6, t7); \
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MOVOU (5*16)(RK), rk128; \
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SM4_8BLOCKS_4ROUNDS(rk128, x, y, z, t0, t1, t2, t3, t4, t5, t6, t7); \
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MOVOU (6*16)(RK), rk128; \
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SM4_8BLOCKS_4ROUNDS(rk128, x, y, z, t0, t1, t2, t3, t4, t5, t6, t7); \
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MOVOU (7*16)(RK), rk128; \
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SM4_8BLOCKS_4ROUNDS(rk128, x, y, z, t0, t1, t2, t3, t4, t5, t6, t7); \
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SSE_TRANSPOSE_MATRIX(t0, t1, t2, t3, x, y); \
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SSE_TRANSPOSE_MATRIX(t4, t5, t6, t7, x, y); \
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PSHUFB bswap_mask<>(SB), t3; \
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PSHUFB bswap_mask<>(SB), t2; \
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PSHUFB bswap_mask<>(SB), t1; \
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PSHUFB bswap_mask<>(SB), t0; \
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PSHUFB bswap_mask<>(SB), t7; \
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|
PSHUFB bswap_mask<>(SB), t6; \
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PSHUFB bswap_mask<>(SB), t5; \
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PSHUFB bswap_mask<>(SB), t4
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|
|
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// SM4 sbox function, AVX version
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// parameters:
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// - x: 128 bits register as sbox input/output data
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// - y: 128 bits temp register
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// - tmp: 128 bits temp register
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#define AVX_SM4_SBOX(x, y, tmp) \
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VPAND nibble_mask<>(SB), x, tmp; \
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VMOVDQU m1_low<>(SB), y; \
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VPSHUFB tmp, y, y; \
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VPSRLQ $4, x, x; \
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VPAND nibble_mask<>(SB), x, x; \
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VMOVDQU m1_high<>(SB), tmp; \
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VPSHUFB x, tmp, x; \
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VPXOR y, x, x; \
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VPSHUFB inverse_shift_rows<>(SB), x, x; \
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VAESENCLAST nibble_mask<>(SB), x, x; \
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VPANDN nibble_mask<>(SB), x, tmp; \
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VMOVDQU m2_low<>(SB), y; \
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VPSHUFB tmp, y, y; \
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VPSRLQ $4, x, x; \
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VPAND nibble_mask<>(SB), x, x; \
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VMOVDQU m2_high<>(SB), tmp; \
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VPSHUFB x, tmp, x; \
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VPXOR y, x, x
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|
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|
// SM4 TAO L1 function, AVX version
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|
// parameters:
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|
// - x: 128 bits register as sbox input/output data
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// - y: 128 bits temp register
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// - tmp: 128 bits temp register
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#define AVX_SM4_TAO_L1(x, y, tmp) \
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AVX_SM4_SBOX(x, y, tmp); \
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VPSHUFB r08_mask<>(SB), x, y; \
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VPXOR x, y, y; \
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VPSHUFB r16_mask<>(SB), x, tmp; \
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VPXOR tmp, y, y; \
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VPSLLD $2, y, tmp; \
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VPSRLD $30, y, y; \
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VPXOR tmp, y, y; \
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VPSHUFB r24_mask<>(SB), x, tmp; \
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VPXOR y, x, x; \
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VPXOR x, tmp, x
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|
|
|
// transpose matrix function, AVX/AVX2 version
|
|
// parameters:
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|
// - r0: 128/256 bits register as input/output data
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// - r1: 128/256 bits register as input/output data
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// - r2: 128/256 bits register as input/output data
|
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// - r3: 128/256 bits register as input/output data
|
|
// - tmp1: 128/256 bits temp register
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// - tmp2: 128/256 bits temp register
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#define TRANSPOSE_MATRIX(r0, r1, r2, r3, tmp1, tmp2) \
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VPUNPCKHDQ r1, r0, tmp2; \ // tmp2 = [w15, w7, w14, w6, w11, w3, w10, w2] tmp2 = [w7, w3, w6, w2]
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VPUNPCKLDQ r1, r0, r0; \ // r0 = [w13, w5, w12, w4, w9, w1, w8, w0] r0 = [w5, w1, w4, w0]
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VPUNPCKLDQ r3, r2, tmp1; \ // tmp1 = [w29, w21, w28, w20, w25, w17, w24, w16] tmp1 = [w13, w9, w12, w8]
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VPUNPCKHDQ r3, r2, r2; \ // r2 = [w31, w27, w30, w22, w27, w19, w26, w18] r2 = [w15, w11, w14, w10]
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VPUNPCKHQDQ tmp1, r0, r1; \ // r1 = [w29, w21, w13, w5, w25, w17, w9, w1] r1 = [w13, w9, w5, w1]
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VPUNPCKLQDQ tmp1, r0, r0; \ // r0 = [w28, w20, w12, w4, w24, w16, w8, w0] r0 = [w12, w8, w4, w0]
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VPUNPCKHQDQ r2, tmp2, r3; \ // r3 = [w31, w27, w15, w7, w27, w19, w11, w3] r3 = [w15, w11, w7, w3]
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VPUNPCKLQDQ r2, tmp2, r2 // r2 = [w30, w22, w14, w6, w26, w18, w10, w2] r2 = [w14, w10, w6, w2]
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|
|
|
// SM4 round function, AVX version, handle 128 bits
|
|
// t0 ^= tao_l1(t1^t2^t3^xk)
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|
// parameters:
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|
// - index: round key index immediate number
|
|
// - x: 128 bits temp register
|
|
// - y: 128 bits temp register
|
|
// - t0: 128 bits register for data as result
|
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// - t1: 128 bits register for data
|
|
// - t2: 128 bits register for data
|
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// - t3: 128 bits register for data
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#define AVX_SM4_ROUND(index, RK, IND, x, y, tmp, t0, t1, t2, t3) \
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MOVL (index * 4)(RK)(IND*1), x; \
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|
VPSHUFD $0, x, x; \
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VPXOR t1, x, x; \
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VPXOR t2, x, x; \
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VPXOR t3, x, x; \
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AVX_SM4_TAO_L1(x, y, tmp); \
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VPXOR x, t0, t0
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|
|
|
|
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#define SM4_ONE_ROUND_AVX(x, y, z, t0, t1, t2, t3) \
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|
VPXOR t1, x, x; \
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VPXOR t2, x, x; \
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|
VPXOR t3, x, x; \
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|
AVX_SM4_TAO_L1(x, y, z); \
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VPXOR x, t0, t0 \
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|
|
|
#define SM4_4BLOCKS_4ROUNDS_AVX(rk128, x, y, z, t0, t1, t2, t3) \
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|
VPSHUFD $0, rk128, x; \
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SM4_ONE_ROUND_AVX(x, y, z, t0, t1, t2, t3); \
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VPSHUFD $0x55, rk128, x; \
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SM4_ONE_ROUND_AVX(x, y, z, t1, t2, t3, t0); \
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VPSHUFD $0xAA, rk128, x; \
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SM4_ONE_ROUND_AVX(x, y, z, t2, t3, t0, t1); \
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|
VPSHUFD $0xFF, rk128, x; \
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SM4_ONE_ROUND_AVX(x, y, z, t3, t0, t1, t2); \
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|
|
|
#define AVX_SM4_4BLOCKS(RK, rk128, x, y, z, t0, t1, t2, t3) \
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VPSHUFB flip_mask<>(SB), t0, t0 \
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VPSHUFB flip_mask<>(SB), t1, t1 \
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VPSHUFB flip_mask<>(SB), t2, t2 \
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VPSHUFB flip_mask<>(SB), t3, t3 \
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; \
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AVX_SM4_4BLOCKS_WO_BS(RK, rk128, x, y, z, t0, t1, t2, t3)
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|
|
|
#define AVX_SM4_4BLOCKS_WO_BS(RK, rk128, x, y, z, t0, t1, t2, t3) \
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TRANSPOSE_MATRIX(t0, t1, t2, t3, x, y) \
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VMOVDQU (0*16)(RK), rk128; \
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SM4_4BLOCKS_4ROUNDS_AVX(rk128, x, y, z, t0, t1, t2, t3); \
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VMOVDQU (1*16)(RK), rk128; \
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SM4_4BLOCKS_4ROUNDS_AVX(rk128, x, y, z, t0, t1, t2, t3); \
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VMOVDQU (2*16)(RK), rk128; \
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SM4_4BLOCKS_4ROUNDS_AVX(rk128, x, y, z, t0, t1, t2, t3); \
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VMOVDQU (3*16)(RK), rk128; \
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SM4_4BLOCKS_4ROUNDS_AVX(rk128, x, y, z, t0, t1, t2, t3); \
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VMOVDQU (4*16)(RK), rk128; \
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SM4_4BLOCKS_4ROUNDS_AVX(rk128, x, y, z, t0, t1, t2, t3); \
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VMOVDQU (5*16)(RK), rk128; \
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SM4_4BLOCKS_4ROUNDS_AVX(rk128, x, y, z, t0, t1, t2, t3); \
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VMOVDQU (6*16)(RK), rk128; \
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SM4_4BLOCKS_4ROUNDS_AVX(rk128, x, y, z, t0, t1, t2, t3); \
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VMOVDQU (7*16)(RK), rk128; \
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SM4_4BLOCKS_4ROUNDS_AVX(rk128, x, y, z, t0, t1, t2, t3); \
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|
; \ // Transpose matrix 4 x 4 32bits word
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|
TRANSPOSE_MATRIX(t0, t1, t2, t3, x, y) \
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|
VPSHUFB bswap_mask<>(SB), t0, t0 \
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|
VPSHUFB bswap_mask<>(SB), t1, t1 \
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|
VPSHUFB bswap_mask<>(SB), t2, t2 \
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|
VPSHUFB bswap_mask<>(SB), t3, t3 \
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|
|
|
#define SM4_8BLOCKS_4ROUNDS_AVX(rk128, x, y, z, t0, t1, t2, t3, t4, t5, t6, t7) \
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VPSHUFD $0, rk128, x; \
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|
SM4_ONE_ROUND_AVX(x, y, z, t0, t1, t2, t3); \
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|
VPSHUFD $0, rk128, x; \
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|
SM4_ONE_ROUND_AVX(x, y, z, t4, t5, t6, t7); \
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|
VPSHUFD $0x55, rk128, x; \
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|
SM4_ONE_ROUND_AVX(x, y, z, t1, t2, t3, t0); \
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|
VPSHUFD $0x55, rk128, x; \
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|
SM4_ONE_ROUND_AVX(x, y, z, t5, t6, t7, t4); \
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|
VPSHUFD $0xAA, rk128, x; \
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|
SM4_ONE_ROUND_AVX(x, y, z, t2, t3, t0, t1); \
|
|
VPSHUFD $0xAA, rk128, x; \
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|
SM4_ONE_ROUND_AVX(x, y, z, t6, t7, t4, t5); \
|
|
VPSHUFD $0xFF, rk128, x; \
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|
SM4_ONE_ROUND_AVX(x, y, z, t3, t0, t1, t2); \
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|
VPSHUFD $0xFF, rk128, x; \
|
|
SM4_ONE_ROUND_AVX(x, y, z, t7, t4, t5, t6); \
|
|
|
|
#define AVX_SM4_8BLOCKS(RK, rk128, x, y, z, t0, t1, t2, t3, t4, t5, t6, t7) \
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|
VPSHUFB flip_mask<>(SB), t0, t0 \
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|
VPSHUFB flip_mask<>(SB), t1, t1 \
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|
VPSHUFB flip_mask<>(SB), t2, t2 \
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|
VPSHUFB flip_mask<>(SB), t3, t3 \
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|
VPSHUFB flip_mask<>(SB), t4, t4 \
|
|
VPSHUFB flip_mask<>(SB), t5, t5 \
|
|
VPSHUFB flip_mask<>(SB), t6, t6 \
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|
VPSHUFB flip_mask<>(SB), t7, t7 \
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|
; \
|
|
AVX_SM4_8BLOCKS_WO_BS(RK, rk128, x, y, z, t0, t1, t2, t3, t4, t5, t6, t7)
|
|
|
|
#define AVX_SM4_8BLOCKS_WO_BS(RK, rk128, x, y, z, t0, t1, t2, t3, t4, t5, t6, t7) \
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|
TRANSPOSE_MATRIX(t0, t1, t2, t3, x, y) \
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|
TRANSPOSE_MATRIX(t4, t5, t6, t7, x, y) \
|
|
VMOVDQU (0*16)(RK), rk128; \
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|
SM4_8BLOCKS_4ROUNDS_AVX(rk128, x, y, z, t0, t1, t2, t3, t4, t5, t6, t7); \
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|
VMOVDQU (1*16)(RK), rk128; \
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|
SM4_8BLOCKS_4ROUNDS_AVX(rk128, x, y, z, t0, t1, t2, t3, t4, t5, t6, t7); \
|
|
VMOVDQU (2*16)(RK), rk128; \
|
|
SM4_8BLOCKS_4ROUNDS_AVX(rk128, x, y, z, t0, t1, t2, t3, t4, t5, t6, t7); \
|
|
VMOVDQU (3*16)(RK), rk128; \
|
|
SM4_8BLOCKS_4ROUNDS_AVX(rk128, x, y, z, t0, t1, t2, t3, t4, t5, t6, t7); \
|
|
VMOVDQU (4*16)(RK), rk128; \
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|
SM4_8BLOCKS_4ROUNDS_AVX(rk128, x, y, z, t0, t1, t2, t3, t4, t5, t6, t7); \
|
|
VMOVDQU (5*16)(RK), rk128; \
|
|
SM4_8BLOCKS_4ROUNDS_AVX(rk128, x, y, z, t0, t1, t2, t3, t4, t5, t6, t7); \
|
|
VMOVDQU (6*16)(RK), rk128; \
|
|
SM4_8BLOCKS_4ROUNDS_AVX(rk128, x, y, z, t0, t1, t2, t3, t4, t5, t6, t7); \
|
|
VMOVDQU (7*16)(RK), rk128; \
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|
SM4_8BLOCKS_4ROUNDS_AVX(rk128, x, y, z, t0, t1, t2, t3, t4, t5, t6, t7); \
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|
; \ // Transpose matrix 4 x 4 32bits word
|
|
TRANSPOSE_MATRIX(t0, t1, t2, t3, x, y) \
|
|
TRANSPOSE_MATRIX(t4, t5, t6, t7, x, y) \
|
|
VPSHUFB bswap_mask<>(SB), t0, t0 \
|
|
VPSHUFB bswap_mask<>(SB), t1, t1 \
|
|
VPSHUFB bswap_mask<>(SB), t2, t2 \
|
|
VPSHUFB bswap_mask<>(SB), t3, t3 \
|
|
VPSHUFB bswap_mask<>(SB), t4, t4 \
|
|
VPSHUFB bswap_mask<>(SB), t5, t5 \
|
|
VPSHUFB bswap_mask<>(SB), t6, t6 \
|
|
VPSHUFB bswap_mask<>(SB), t7, t7 \
|
|
|
|
// SM4 sbox function, AVX2 version
|
|
// parameters:
|
|
// - x: 256 bits register as sbox input/output data
|
|
// - y: 256 bits temp register
|
|
// - z: 256 bits temp register
|
|
// - xw: 128 bits temp register
|
|
// - yw: 128 bits temp register
|
|
// - xNibbleMask: 128 bits register stored nibble mask, should be loaded earlier.
|
|
// - yNibbleMask: 256 bits register stored nibble mask, should be loaded earlier.
|
|
#define AVX2_SM4_SBOX(x, y, z, xw, yw, xNibbleMask, yNibbleMask) \
|
|
VPAND yNibbleMask, x, z; \
|
|
VBROADCASTI128 m1_low<>(SB), y; \
|
|
VPSHUFB z, y, y; \
|
|
VPSRLQ $4, x, x; \
|
|
VPAND yNibbleMask, x, x; \
|
|
VBROADCASTI128 m1_high<>(SB), z; \
|
|
VPSHUFB x, z, x; \
|
|
VPXOR y, x, x; \
|
|
VPSHUFB inverse_shift_rows256<>(SB), x, x; \
|
|
VEXTRACTI128 $1, x, yw \
|
|
VAESENCLAST xNibbleMask, xw, xw; \
|
|
VAESENCLAST xNibbleMask, yw, yw; \
|
|
VINSERTI128 $1, yw, x, x; \
|
|
VPANDN yNibbleMask, x, z; \
|
|
VBROADCASTI128 m2_low<>(SB), y; \
|
|
VPSHUFB z, y, y; \
|
|
VPSRLQ $4, x, x; \
|
|
VPAND yNibbleMask, x, x; \
|
|
VBROADCASTI128 m2_high<>(SB), z; \
|
|
VPSHUFB x, z, x; \
|
|
VPXOR y, x, x
|
|
|
|
// SM4 TAO L1 function, AVX2 version
|
|
// parameters:
|
|
// - x: 256 bits register as sbox input/output data
|
|
// - y: 256 bits temp register
|
|
// - z: 256 bits temp register
|
|
// - xw: 128 bits temp register, x's related low 128 bits register!
|
|
// - yw: 128 bits temp register, y's related low 128 bits register!
|
|
// - xNibbleMask: 128 bits register stored nibble mask, should be loaded earlier.
|
|
// - yNibbleMask: 256 bits register stored nibble mask, should be loaded earlier.
|
|
#define AVX2_SM4_TAO_L1(x, y, z, xw, yw, xNibbleMask, yNibbleMask) \
|
|
AVX2_SM4_SBOX(x, y, z, xw, yw, xNibbleMask, yNibbleMask); \
|
|
VPSHUFB r08_mask256<>(SB), x, y; \
|
|
VPXOR x, y, y; \
|
|
VPSHUFB r16_mask256<>(SB), x, z; \
|
|
VPXOR z, y, y; \
|
|
VPSLLD $2, y, z; \
|
|
VPSRLD $30, y, y; \
|
|
VPXOR z, y, y; \
|
|
VPSHUFB r24_mask256<>(SB), x, z; \
|
|
VPXOR y, x, x; \
|
|
VPXOR x, z, x
|
|
|
|
// SM4 round function, AVX2 version, handle 256 bits
|
|
// t0 ^= tao_l1(t1^t2^t3^xk)
|
|
// parameters:
|
|
// - index: round key index immediate number
|
|
// - x: 256 bits temp register, MUST use XDWORD!
|
|
// - y: 256 bits temp register, MUST use YDWORD!
|
|
// - t0: 256 bits register for data as result
|
|
// - t1: 256 bits register for data
|
|
// - t2: 256 bits register for data
|
|
// - t3: 256 bits register for data
|
|
#define AVX2_SM4_ROUND(index, RK, IND, x, y, xw, yw, tmp, t0, t1, t2, t3) \
|
|
VPBROADCASTD (index * 4)(RK)(IND*1), x; \
|
|
VPXOR t1, x, x; \
|
|
VPXOR t2, x, x; \
|
|
VPXOR t3, x, x; \
|
|
AVX2_SM4_TAO_L1(x, y, tmp, xw, yw, X_NIBBLE_MASK, NIBBLE_MASK); \
|
|
VPXOR x, t0, t0
|
|
|
|
// SM4 round function, AVX2 version, handle 256 bits
|
|
// t0 ^= tao_l1(t1^t2^t3^xk)
|
|
// parameters:
|
|
// - index: round key index immediate number
|
|
// - x: 256 bits temp register, MUST use XDWORD!
|
|
// - y: 256 bits temp register, MUST use YDWORD!
|
|
// - t0: 256 bits register for data as result
|
|
// - t1: 256 bits register for data
|
|
// - t2: 256 bits register for data
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// - t3: 256 bits register for data
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#define AVX2_SM4_ROUND2(index, RK, x, y, xw, yw, tmp, t0, t1, t2, t3) \
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VPBROADCASTD (index * 4)(RK), x; \
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VPXOR t1, x, x; \
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VPXOR t2, x, x; \
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VPXOR t3, x, x; \
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AVX2_SM4_TAO_L1(x, y, tmp, xw, yw, X_NIBBLE_MASK, NIBBLE_MASK); \
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VPXOR x, t0, t0
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// SM4 round function, AVX version, handle 128 bits
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// t0 ^= tao_l1(t1^t2^t3^xk)
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// parameters:
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// - index: round key index immediate number
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// - x: 128 bits temp register
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// - y: 128 bits temp register
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// - t0: 128 bits register for data as result
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// - t1: 128 bits register for data
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// - t2: 128 bits register for data
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// - t3: 128 bits register for data
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#define AVX2_SM4_ROUND_4BLOCKS(index, RK, IND, x, y, tmp, t0, t1, t2, t3) \
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VPBROADCASTD (index * 4)(RK)(IND*1), x; \
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VPXOR t1, x, x; \
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VPXOR t2, x, x; \
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VPXOR t3, x, x; \
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AVX_SM4_TAO_L1(x, y, tmp); \
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VPXOR x, t0, t0
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#define AVX2_SM4_8BLOCKS(RK, x, y, xw, yw, tmp, t0, t1, t2, t3) \
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AVX2_SM4_ROUND2(0, RK, x, y, xw, yw, tmp, t0, t1, t2, t3); \
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AVX2_SM4_ROUND2(1, RK, x, y, xw, yw, tmp, t1, t2, t3, t0); \
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AVX2_SM4_ROUND2(2, RK, x, y, xw, yw, tmp, t2, t3, t0, t1); \
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AVX2_SM4_ROUND2(3, RK, x, y, xw, yw, tmp, t3, t0, t1, t2); \
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AVX2_SM4_ROUND2(4, RK, x, y, xw, yw, tmp, t0, t1, t2, t3); \
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AVX2_SM4_ROUND2(5, RK, x, y, xw, yw, tmp, t1, t2, t3, t0); \
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AVX2_SM4_ROUND2(6, RK, x, y, xw, yw, tmp, t2, t3, t0, t1); \
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AVX2_SM4_ROUND2(7, RK, x, y, xw, yw, tmp, t3, t0, t1, t2); \
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AVX2_SM4_ROUND2(8, RK, x, y, xw, yw, tmp, t0, t1, t2, t3); \
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AVX2_SM4_ROUND2(9, RK, x, y, xw, yw, tmp, t1, t2, t3, t0); \
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AVX2_SM4_ROUND2(10, RK, x, y, xw, yw, tmp, t2, t3, t0, t1); \
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AVX2_SM4_ROUND2(11, RK, x, y, xw, yw, tmp, t3, t0, t1, t2); \
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AVX2_SM4_ROUND2(12, RK, x, y, xw, yw, tmp, t0, t1, t2, t3); \
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AVX2_SM4_ROUND2(13, RK, x, y, xw, yw, tmp, t1, t2, t3, t0); \
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AVX2_SM4_ROUND2(14, RK, x, y, xw, yw, tmp, t2, t3, t0, t1); \
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AVX2_SM4_ROUND2(15, RK, x, y, xw, yw, tmp, t3, t0, t1, t2); \
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AVX2_SM4_ROUND2(16, RK, x, y, xw, yw, tmp, t0, t1, t2, t3); \
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AVX2_SM4_ROUND2(17, RK, x, y, xw, yw, tmp, t1, t2, t3, t0); \
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AVX2_SM4_ROUND2(18, RK, x, y, xw, yw, tmp, t2, t3, t0, t1); \
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AVX2_SM4_ROUND2(19, RK, x, y, xw, yw, tmp, t3, t0, t1, t2); \
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AVX2_SM4_ROUND2(20, RK, x, y, xw, yw, tmp, t0, t1, t2, t3); \
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AVX2_SM4_ROUND2(21, RK, x, y, xw, yw, tmp, t1, t2, t3, t0); \
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AVX2_SM4_ROUND2(22, RK, x, y, xw, yw, tmp, t2, t3, t0, t1); \
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AVX2_SM4_ROUND2(23, RK, x, y, xw, yw, tmp, t3, t0, t1, t2); \
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AVX2_SM4_ROUND2(24, RK, x, y, xw, yw, tmp, t0, t1, t2, t3); \
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AVX2_SM4_ROUND2(25, RK, x, y, xw, yw, tmp, t1, t2, t3, t0); \
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AVX2_SM4_ROUND2(26, RK, x, y, xw, yw, tmp, t2, t3, t0, t1); \
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AVX2_SM4_ROUND2(27, RK, x, y, xw, yw, tmp, t3, t0, t1, t2); \
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AVX2_SM4_ROUND2(28, RK, x, y, xw, yw, tmp, t0, t1, t2, t3); \
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AVX2_SM4_ROUND2(29, RK, x, y, xw, yw, tmp, t1, t2, t3, t0); \
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AVX2_SM4_ROUND2(30, RK, x, y, xw, yw, tmp, t2, t3, t0, t1); \
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AVX2_SM4_ROUND2(31, RK, x, y, xw, yw, tmp, t3, t0, t1, t2)
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// SM4 round function, AVX2 version, handle 256 bits
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// t0 ^= tao_l1(t1^t2^t3^xk)
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// parameters:
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// - index: round key index immediate number
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// - x: 256 bits temp register, MUST use XDWORD!
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// - y: 256 bits temp register, MUST use YDWORD!
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// - t0: 256 bits register for data as result
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// - t1: 256 bits register for data
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// - t2: 256 bits register for data
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// - t3: 256 bits register for data
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#define AVX2_SM4_16BLOCKS_ROUND(index, RK, x, y, xw, yw, tmp, tmp1, t0, t1, t2, t3, t4, t5, t6, t7) \
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VPBROADCASTD (index * 4)(RK), tmp1; \
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VPXOR t1, tmp1, x; \
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VPXOR t2, x, x; \
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VPXOR t3, x, x; \
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AVX2_SM4_TAO_L1(x, y, tmp, xw, yw, X_NIBBLE_MASK, NIBBLE_MASK); \
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VPXOR x, t0, t0; \
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;\
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VPXOR t5, tmp1, x; \
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VPXOR t6, x, x; \
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VPXOR t7, x, x; \
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AVX2_SM4_TAO_L1(x, y, tmp, xw, yw, X_NIBBLE_MASK, NIBBLE_MASK); \
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VPXOR x, t4, t4; \
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#define AVX2_SM4_16BLOCKS(RK, x, y, xw, yw, tmp, tmp1, t0, t1, t2, t3, t4, t5, t6, t7) \
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AVX2_SM4_16BLOCKS_ROUND(0, RK, x, y, xw, yw, tmp, tmp1, t0, t1, t2, t3, t4, t5, t6, t7); \
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AVX2_SM4_16BLOCKS_ROUND(1, RK, x, y, xw, yw, tmp, tmp1, t1, t2, t3, t0, t5, t6, t7, t4); \
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AVX2_SM4_16BLOCKS_ROUND(2, RK, x, y, xw, yw, tmp, tmp1, t2, t3, t0, t1, t6, t7, t4, t5); \
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AVX2_SM4_16BLOCKS_ROUND(3, RK, x, y, xw, yw, tmp, tmp1, t3, t0, t1, t2, t7, t4, t5, t6); \
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AVX2_SM4_16BLOCKS_ROUND(4, RK, x, y, xw, yw, tmp, tmp1, t0, t1, t2, t3, t4, t5, t6, t7); \
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AVX2_SM4_16BLOCKS_ROUND(5, RK, x, y, xw, yw, tmp, tmp1, t1, t2, t3, t0, t5, t6, t7, t4); \
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AVX2_SM4_16BLOCKS_ROUND(6, RK, x, y, xw, yw, tmp, tmp1, t2, t3, t0, t1, t6, t7, t4, t5); \
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AVX2_SM4_16BLOCKS_ROUND(7, RK, x, y, xw, yw, tmp, tmp1, t3, t0, t1, t2, t7, t4, t5, t6); \
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AVX2_SM4_16BLOCKS_ROUND(8, RK, x, y, xw, yw, tmp, tmp1, t0, t1, t2, t3, t4, t5, t6, t7); \
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AVX2_SM4_16BLOCKS_ROUND(9, RK, x, y, xw, yw, tmp, tmp1, t1, t2, t3, t0, t5, t6, t7, t4); \
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AVX2_SM4_16BLOCKS_ROUND(10, RK, x, y, xw, yw, tmp, tmp1, t2, t3, t0, t1, t6, t7, t4, t5); \
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AVX2_SM4_16BLOCKS_ROUND(11, RK, x, y, xw, yw, tmp, tmp1, t3, t0, t1, t2, t7, t4, t5, t6); \
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AVX2_SM4_16BLOCKS_ROUND(12, RK, x, y, xw, yw, tmp, tmp1, t0, t1, t2, t3, t4, t5, t6, t7); \
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AVX2_SM4_16BLOCKS_ROUND(13, RK, x, y, xw, yw, tmp, tmp1, t1, t2, t3, t0, t5, t6, t7, t4); \
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AVX2_SM4_16BLOCKS_ROUND(14, RK, x, y, xw, yw, tmp, tmp1, t2, t3, t0, t1, t6, t7, t4, t5); \
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AVX2_SM4_16BLOCKS_ROUND(15, RK, x, y, xw, yw, tmp, tmp1, t3, t0, t1, t2, t7, t4, t5, t6); \
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AVX2_SM4_16BLOCKS_ROUND(16, RK, x, y, xw, yw, tmp, tmp1, t0, t1, t2, t3, t4, t5, t6, t7); \
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AVX2_SM4_16BLOCKS_ROUND(17, RK, x, y, xw, yw, tmp, tmp1, t1, t2, t3, t0, t5, t6, t7, t4); \
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AVX2_SM4_16BLOCKS_ROUND(18, RK, x, y, xw, yw, tmp, tmp1, t2, t3, t0, t1, t6, t7, t4, t5); \
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AVX2_SM4_16BLOCKS_ROUND(19, RK, x, y, xw, yw, tmp, tmp1, t3, t0, t1, t2, t7, t4, t5, t6); \
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AVX2_SM4_16BLOCKS_ROUND(20, RK, x, y, xw, yw, tmp, tmp1, t0, t1, t2, t3, t4, t5, t6, t7); \
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AVX2_SM4_16BLOCKS_ROUND(21, RK, x, y, xw, yw, tmp, tmp1, t1, t2, t3, t0, t5, t6, t7, t4); \
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AVX2_SM4_16BLOCKS_ROUND(22, RK, x, y, xw, yw, tmp, tmp1, t2, t3, t0, t1, t6, t7, t4, t5); \
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AVX2_SM4_16BLOCKS_ROUND(23, RK, x, y, xw, yw, tmp, tmp1, t3, t0, t1, t2, t7, t4, t5, t6); \
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AVX2_SM4_16BLOCKS_ROUND(24, RK, x, y, xw, yw, tmp, tmp1, t0, t1, t2, t3, t4, t5, t6, t7); \
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AVX2_SM4_16BLOCKS_ROUND(25, RK, x, y, xw, yw, tmp, tmp1, t1, t2, t3, t0, t5, t6, t7, t4); \
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AVX2_SM4_16BLOCKS_ROUND(26, RK, x, y, xw, yw, tmp, tmp1, t2, t3, t0, t1, t6, t7, t4, t5); \
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AVX2_SM4_16BLOCKS_ROUND(27, RK, x, y, xw, yw, tmp, tmp1, t3, t0, t1, t2, t7, t4, t5, t6); \
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AVX2_SM4_16BLOCKS_ROUND(28, RK, x, y, xw, yw, tmp, tmp1, t0, t1, t2, t3, t4, t5, t6, t7); \
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AVX2_SM4_16BLOCKS_ROUND(29, RK, x, y, xw, yw, tmp, tmp1, t1, t2, t3, t0, t5, t6, t7, t4); \
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AVX2_SM4_16BLOCKS_ROUND(30, RK, x, y, xw, yw, tmp, tmp1, t2, t3, t0, t1, t6, t7, t4, t5); \
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AVX2_SM4_16BLOCKS_ROUND(31, RK, x, y, xw, yw, tmp, tmp1, t3, t0, t1, t2, t7, t4, t5, t6)
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