mirror of
https://github.com/emmansun/gmsm.git
synced 2025-04-22 02:06:18 +08:00
365 lines
15 KiB
C
365 lines
15 KiB
C
// shuffle byte order from LE to BE
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DATA flip_mask<>+0x00(SB)/8, $0x0405060700010203
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DATA flip_mask<>+0x08(SB)/8, $0x0c0d0e0f08090a0b
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GLOBL flip_mask<>(SB), RODATA, $16
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// shuffle byte and word order
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DATA bswap_mask<>+0x00(SB)/8, $0x08090a0b0c0d0e0f
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DATA bswap_mask<>+0x08(SB)/8, $0x0001020304050607
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GLOBL bswap_mask<>(SB), RODATA, $16
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//nibble mask
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DATA nibble_mask<>+0x00(SB)/8, $0x0F0F0F0F0F0F0F0F
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DATA nibble_mask<>+0x08(SB)/8, $0x0F0F0F0F0F0F0F0F
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GLOBL nibble_mask<>(SB), RODATA, $16
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// inverse shift rows
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DATA inverse_shift_rows<>+0x00(SB)/8, $0x0B0E0104070A0D00
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DATA inverse_shift_rows<>+0x08(SB)/8, $0x0306090C0F020508
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GLOBL inverse_shift_rows<>(SB), RODATA, $16
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// Affine transform 1 (low and high hibbles)
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DATA m1_low<>+0x00(SB)/8, $0x0A7FC3B6D5A01C69
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DATA m1_low<>+0x08(SB)/8, $0x3045F98CEF9A2653
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GLOBL m1_low<>(SB), RODATA, $16
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DATA m1_high<>+0x00(SB)/8, $0xC35BF46CAF379800
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DATA m1_high<>+0x08(SB)/8, $0x68F05FC7049C33AB
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GLOBL m1_high<>(SB), RODATA, $16
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// Affine transform 2 (low and high hibbles)
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DATA m2_low<>+0x00(SB)/8, $0x9A950A05FEF16E61
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DATA m2_low<>+0x08(SB)/8, $0x0E019E916A65FAF5
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GLOBL m2_low<>(SB), RODATA, $16
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DATA m2_high<>+0x00(SB)/8, $0x892D69CD44E0A400
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DATA m2_high<>+0x08(SB)/8, $0x2C88CC68E14501A5
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GLOBL m2_high<>(SB), RODATA, $16
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// left rotations of 32-bit words by 8-bit increments
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DATA r08_mask<>+0x00(SB)/8, $0x0605040702010003
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DATA r08_mask<>+0x08(SB)/8, $0x0E0D0C0F0A09080B
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GLOBL r08_mask<>(SB), RODATA, $16
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DATA r16_mask<>+0x00(SB)/8, $0x0504070601000302
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DATA r16_mask<>+0x08(SB)/8, $0x0D0C0F0E09080B0A
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GLOBL r16_mask<>(SB), RODATA, $16
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DATA r24_mask<>+0x00(SB)/8, $0x0407060500030201
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DATA r24_mask<>+0x08(SB)/8, $0x0C0F0E0D080B0A09
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GLOBL r24_mask<>(SB), RODATA, $16
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DATA fk_mask<>+0x00(SB)/8, $0x56aa3350a3b1bac6
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DATA fk_mask<>+0x08(SB)/8, $0xb27022dc677d9197
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GLOBL fk_mask<>(SB), RODATA, $16
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// Transpose matrix without PUNPCKHDQ/PUNPCKLDQ/PUNPCKHQDQ/PUNPCKLQDQ instructions, bad performance!
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// input: from high to low
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// r0 = [w3, w2, w1, w0]
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// r1 = [w7, w6, w5, w4]
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// r2 = [w11, w10, w9, w8]
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// r3 = [w15, w14, w13, w12]
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// r: 32/64 temp register
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// tmp1: 128 bits temp register
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// tmp2: 128 bits temp register
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//
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// output: from high to low
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// r0 = [w12, w8, w4, w0]
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// r1 = [w13, w9, w5, w1]
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// r2 = [w14, w10, w6, w2]
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// r3 = [w15, w11, w7, w3]
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//
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// SSE2/MMX instructions:
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// MOVOU r0, tmp2;
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// PUNPCKHDQ r1, tmp2;
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// PUNPCKLDQ r1, r0;
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// MOVOU r2, tmp1;
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// PUNPCKLDQ r3, tmp1;
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// PUNPCKHDQ r3, r2;
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// MOVOU r0, r1;
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// PUNPCKHQDQ tmp1, r1;
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// PUNPCKLQDQ tmp1, r0;
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// MOVOU tmp2, r3;
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// PUNPCKHQDQ r2, r3;
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// PUNPCKLQDQ r2, tmp2;
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// MOVOU tmp2, r2
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#define SSE_TRANSPOSE_MATRIX(r, r0, r1, r2, r3, tmp1, tmp2) \
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PEXTRD $2, r0, r; \
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PINSRD $0, r, tmp2; \
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PEXTRD $2, r1, r; \
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PINSRD $1, r, tmp2; \
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; \
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PEXTRD $3, r0, r; \
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PINSRD $2, r, tmp2; \
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PEXTRD $3, r1, r; \
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PINSRD $3, r, tmp2; \ // tmp2 = [w7, w3, w6, w2]
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; \
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PEXTRD $1, r0, r; \
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PINSRD $2, r, r0; \
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PEXTRD $0, r1, r; \
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PINSRD $1, r, r0; \
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PEXTRD $1, r1, r; \
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PINSRD $3, r, r0; \ // r0 = [w5, w1, w4, w0]
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; \
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PEXTRD $0, r2, r; \
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PINSRD $0, r, tmp1; \
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PEXTRD $0, r3, r; \
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PINSRD $1, r, tmp1; \
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PEXTRD $1, r2, r; \
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PINSRD $2, r, tmp1; \
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PEXTRD $1, r3, r; \
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PINSRD $3, r, tmp1; \ // tmp1 = [w13, w9, w12, w8]
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; \
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PEXTRD $2, r2, r; \
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PINSRD $0, r, r2; \
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PEXTRD $2, r3, r; \
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PINSRD $1, r, r2; \
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PEXTRD $3, r2, r; \
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PINSRD $2, r, r2; \
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PEXTRD $3, r3, r; \
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PINSRD $3, r, r2; \ // r2 = [w15, w11, w14, w10]
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; \
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MOVOU r0, r1; \
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PEXTRQ $1, r1, r; \
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PINSRQ $0, r, r1; \
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PEXTRQ $1, tmp1, r; \
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PINSRQ $1, r, r1; \ // r1 = [w13, w9, w5, w1]
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; \
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PEXTRQ $0, tmp1, r; \
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PINSRQ $1, r, r0; \ // r0 = [w12, w8, w4, w0]
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; \
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MOVOU tmp2, r3; \
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PEXTRQ $1, r3, r; \
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PINSRQ $0, r, r3; \
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PEXTRQ $1, r2, r; \
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PINSRQ $1, r, r3; \ // r3 = [w15, w11, w7, w3]
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; \
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PEXTRQ $0, r2, r; \
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PINSRQ $1, r, r2; \
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PEXTRQ $0, tmp2, r; \
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PINSRQ $0, r, r2
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// SM4 sbox function
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// parameters:
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// - x: 128 bits register as sbox input/output data
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// - y: 128 bits temp register
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// - z: 128 bits temp register
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#define SM4_SBOX(x, y, z) \
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; \ //############################# inner affine ############################//
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MOVOU x, z; \
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PAND nibble_mask<>(SB), z; \ //y = _mm_and_si128(x, c0f);
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MOVOU m1_low<>(SB), y; \
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PSHUFB z, y; \ //y = _mm_shuffle_epi8(m1l, y);
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PSRLQ $4, x; \ //x = _mm_srli_epi64(x, 4);
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PAND nibble_mask<>(SB), x; \ //x = _mm_and_si128(x, c0f);
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MOVOU m1_high<>(SB), z; \
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PSHUFB x, z; \ //x = _mm_shuffle_epi8(m1h, x);
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MOVOU z, x; \ //x = _mm_shuffle_epi8(m1h, x);
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PXOR y, x; \ //x = _mm_shuffle_epi8(m1h, x) ^ y;
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; \ // inverse ShiftRows
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PSHUFB inverse_shift_rows<>(SB), x; \ //x = _mm_shuffle_epi8(x, shr);
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AESENCLAST nibble_mask<>(SB), x; \ // AESNI instruction
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; \ //############################# outer affine ############################//
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MOVOU x, z; \
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PANDN nibble_mask<>(SB), z; \ //z = _mm_andnot_si128(x, c0f);
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MOVOU m2_low<>(SB), y; \
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PSHUFB z, y; \ //y = _mm_shuffle_epi8(m2l, z)
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PSRLQ $4, x; \ //x = _mm_srli_epi64(x, 4);
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PAND nibble_mask<>(SB), x; \ //x = _mm_and_si128(x, c0f);
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MOVOU m2_high<>(SB), z; \
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PSHUFB x, z; \
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MOVOU z, x; \ //x = _mm_shuffle_epi8(m2h, x)
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PXOR y, x //x = _mm_shuffle_epi8(m2h, x) ^ y;
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// SM4 TAO L1 function
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// parameters:
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// - x: 128 bits register as TAO_L1 input/output data
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// - y: 128 bits temp register
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// - z: 128 bits temp register
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#define SM4_TAO_L1(x, y, z) \
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SM4_SBOX(x, y, z); \
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; \ //#################### 4 parallel L1 linear transforms ##################//
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MOVOU x, y; \
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PSHUFB r08_mask<>(SB), y; \ //y = _mm_shuffle_epi8(x, r08)
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PXOR x, y; \ //y = x xor _mm_shuffle_epi8(x, r08)
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MOVOU x, z; \
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PSHUFB r16_mask<>(SB), z; \
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PXOR z, y; \ //y = x xor _mm_shuffle_epi8(x, r08) xor _mm_shuffle_epi8(x, r16)
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MOVOU y, z; \
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PSLLL $2, z; \
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PSRLL $30, y; \
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POR z, y; \ //y = _mm_slli_epi32(y, 2) ^ _mm_srli_epi32(y, 30);
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MOVOU x, z; \
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PSHUFB r24_mask<>(SB), z; \
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PXOR y, x; \ //x = x xor y
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PXOR z, x //x = x xor y xor _mm_shuffle_epi8(x, r24);
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// SM4 single round function, handle 16 bytes data
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// t0 ^= tao_l1(t1^t2^t3^xk)
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// used R19 as temp 32/64 bits register
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// parameters:
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// - index: round key index immediate number
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// - RK: round key register
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// - IND: round key index base register
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// - x: 128 bits temp register
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// - y: 128 bits temp register
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// - z: 128 bits temp register
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// - t0: 128 bits register for data as result
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// - t1: 128 bits register for data
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// - t2: 128 bits register for data
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// - t3: 128 bits register for data
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#define SM4_SINGLE_ROUND(index, RK, IND, x, y, z, t0, t1, t2, t3) \
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PINSRD $0, (index * 4)(RK)(IND*1), x; \
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PXOR t1, x; \
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PXOR t2, x; \
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PXOR t3, x; \
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SM4_TAO_L1(x, y, z); \
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PXOR x, t0
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// SM4 round function, handle 64 bytes data
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// t0 ^= tao_l1(t1^t2^t3^xk)
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// parameters:
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// - index: round key index immediate number
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// - RK: round key register
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// - IND: round key index base register
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// - x: 128 bits temp register
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// - y: 128 bits temp register
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// - z: 128 bits temp register
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// - t0: 128 bits register for data as result
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// - t1: 128 bits register for data
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// - t2: 128 bits register for data
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// - t3: 128 bits register for data
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#define SM4_ROUND(index, RK, IND, x, y, z, t0, t1, t2, t3) \
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PINSRD $0, (index * 4)(RK)(IND*1), x; \
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PSHUFD $0, x, x; \
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PXOR t1, x; \
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PXOR t2, x; \
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PXOR t3, x; \
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SM4_TAO_L1(x, y, z); \
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PXOR x, t0
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// SM4 sbox function, AVX version
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// parameters:
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// - x: 128 bits register as sbox input/output data
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// - y: 128 bits temp register
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// - X_NIBBLE_MASK: 128 bits register stored nibble mask, should be loaded earlier.
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// - tmp: 128 bits temp register
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#define AVX_SM4_SBOX(x, y, X_NIBBLE_MASK, tmp) \
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VPAND X_NIBBLE_MASK, x, tmp; \
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VMOVDQU m1_low<>(SB), y; \
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VPSHUFB tmp, y, y; \
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VPSRLQ $4, x, x; \
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VPAND X_NIBBLE_MASK, x, x; \
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VMOVDQU m1_high<>(SB), tmp; \
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VPSHUFB x, tmp, x; \
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VPXOR y, x, x; \
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VMOVDQU inverse_shift_rows<>(SB), tmp; \
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VPSHUFB tmp, x, x; \
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VAESENCLAST X_NIBBLE_MASK, x, x; \
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VPANDN X_NIBBLE_MASK, x, tmp; \
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VMOVDQU m2_low<>(SB), y; \
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VPSHUFB tmp, y, y; \
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VPSRLQ $4, x, x; \
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VPAND X_NIBBLE_MASK, x, x; \
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VMOVDQU m2_high<>(SB), tmp; \
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VPSHUFB x, tmp, x; \
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VPXOR y, x, x
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// SM4 TAO L1 function, AVX version
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// parameters:
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// - x: 128 bits register as sbox input/output data
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// - y: 128 bits temp register
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// - xNibbleMask: 128 bits register stored nibble mask, should be loaded earlier.
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// - tmp: 128 bits temp register
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#define AVX_SM4_TAO_L1(x, y, xNibbleMask, tmp) \
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AVX_SM4_SBOX(x, y, xNibbleMask, tmp); \
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VMOVDQU r08_mask<>(SB), tmp; \
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VPSHUFB tmp, x, y; \
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VPXOR x, y, y; \
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VMOVDQU r16_mask<>(SB), tmp; \
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VPSHUFB tmp, x, tmp; \
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VPXOR tmp, y, y; \
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VPSLLD $2, y, tmp; \
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VPSRLD $30, y, y; \
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VPXOR tmp, y, y; \
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VMOVDQU r24_mask<>(SB), tmp; \
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VPSHUFB tmp, x, tmp; \
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VPXOR y, x, x; \
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VPXOR x, tmp, x
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// transpose matrix function, AVX/AVX2 version
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// parameters:
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// - r0: 128/256 bits register as input/output data
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// - r1: 128/256 bits register as input/output data
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// - r2: 128/256 bits register as input/output data
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// - r3: 128/256 bits register as input/output data
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// - tmp1: 128/256 bits temp register
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// - tmp2: 128/256 bits temp register
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#define TRANSPOSE_MATRIX(r0, r1, r2, r3, tmp1, tmp2) \
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VPUNPCKHDQ r1, r0, tmp2; \ // tmp2 = [w15, w7, w14, w6, w11, w3, w10, w2] tmp2 = [w7, w3, w6, w2]
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VPUNPCKLDQ r1, r0, r0; \ // r0 = [w13, w5, w12, w4, w9, w1, w8, w0] r0 = [w5, w1, w4, w0]
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VPUNPCKLDQ r3, r2, tmp1; \ // tmp1 = [w29, w21, w28, w20, w25, w17, w24, w16] tmp1 = [w13, w9, w12, w8]
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VPUNPCKHDQ r3, r2, r2; \ // r2 = [w31, w27, w30, w22, w27, w19, w26, w18] r2 = [w15, w11, w14, w10]
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VPUNPCKHQDQ tmp1, r0, r1; \ // r1 = [w29, w21, w13, w5, w25, w17, w9, w1] r1 = [w13, w9, w5, w1]
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VPUNPCKLQDQ tmp1, r0, r0; \ // r0 = [w28, w20, w12, w4, w24, w16, w8, w0] r0 = [w12, w8, w4, w0]
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VPUNPCKHQDQ r2, tmp2, r3; \ // r3 = [w31, w27, w15, w7, w27, w19, w11, w3] r3 = [w15, w11, w7, w3]
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VPUNPCKLQDQ r2, tmp2, r2 // r2 = [w30, w22, w14, w6, w26, w18, w10, w2] r2 = [w14, w10, w6, w2]
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// SM4 sbox function, AVX2 version
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// parameters:
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// - x: 256 bits register as sbox input/output data
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// - y: 256 bits temp register
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// - z: 256 bits temp register
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// - xw: 128 bits temp register
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// - yw: 128 bits temp register
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// - xNibbleMask: 128 bits register stored nibble mask, should be loaded earlier.
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// - yNibbleMask: 256 bits register stored nibble mask, should be loaded earlier.
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#define AVX2_SM4_SBOX(x, y, z, xw, yw, xNibbleMask, yNibbleMask) \
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VPAND yNibbleMask, x, z; \
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VBROADCASTI128 m1_low<>(SB), y; \
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VPSHUFB z, y, y; \
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VPSRLQ $4, x, x; \
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VPAND yNibbleMask, x, x; \
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VBROADCASTI128 m1_high<>(SB), z; \
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VPSHUFB x, z, x; \
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VPXOR y, x, x; \
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VBROADCASTI128 inverse_shift_rows<>(SB), z; \
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VPSHUFB z, x, x; \
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VEXTRACTI128 $1, x, yw \
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VAESENCLAST xNibbleMask, xw, xw; \
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VAESENCLAST xNibbleMask, yw, yw; \
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VINSERTI128 $1, yw, x, x; \
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VPANDN yNibbleMask, x, z; \
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VBROADCASTI128 m2_low<>(SB), y; \
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VPSHUFB z, y, y; \
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VPSRLQ $4, x, x; \
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VPAND yNibbleMask, x, x; \
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VBROADCASTI128 m2_high<>(SB), z; \
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VPSHUFB x, z, x; \
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VPXOR y, x, x
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// SM4 TAO L1 function, AVX2 version
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// parameters:
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// - x: 256 bits register as sbox input/output data
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// - y: 256 bits temp register
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// - z: 256 bits temp register
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// - xw: 128 bits temp register
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// - yw: 128 bits temp register
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// - xNibbleMask: 128 bits register stored nibble mask, should be loaded earlier.
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// - yNibbleMask: 256 bits register stored nibble mask, should be loaded earlier.
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#define AVX2_SM4_TAO_L1(x, y, z, xw, yw, xNibbleMask, yNibbleMask) \
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AVX2_SM4_SBOX(x, y, z, xw, yw, xNibbleMask, yNibbleMask); \
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VBROADCASTI128 r08_mask<>(SB), z; \
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VPSHUFB z, x, y; \
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VPXOR x, y, y; \
|
|
VBROADCASTI128 r16_mask<>(SB), z; \
|
|
VPSHUFB z, x, z; \
|
|
VPXOR z, y, y; \
|
|
VPSLLD $2, y, z; \
|
|
VPSRLD $30, y, y; \
|
|
VPXOR z, y, y; \
|
|
VBROADCASTI128 r24_mask<>(SB), z; \
|
|
VPSHUFB z, x, z; \
|
|
VPXOR y, x, x; \
|
|
VPXOR x, z, x
|