mirror of
https://github.com/emmansun/gmsm.git
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232 lines
5.1 KiB
ArmAsm
232 lines
5.1 KiB
ArmAsm
// Copyright 2024 Sun Yimin. All rights reserved.
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// Use of this source code is governed by a MIT-style
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// license that can be found in the LICENSE file.
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//go:build (ppc64 || ppc64le) && !purego
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#include "textflag.h"
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#define REVERSE_WORDS V19
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#define M1L V20
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#define M1H V21
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#define M2L V22
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#define M2H V23
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#define V_FOUR V24
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#define NIBBLE_MASK V29
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// For instruction emulation
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#define ESPERMW V31 // Endian swapping permute into BE
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#define TMP0 V10
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#define TMP1 V11
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#define TMP2 V12
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#define TMP3 V13
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#include "aesni_macros_ppc64x.s"
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// func encryptSm4Ecb(xk *uint32, dst, src []byte)
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TEXT ·encryptSm4Ecb(SB),NOSPLIT,$0
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#define dstPtr R3
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#define srcPtr R4
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#define rk R5
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#define srcLen R6
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// prepare/load constants
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VSPLTISB $4, V_FOUR;
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#ifdef NEEDS_PERMW
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MOVD $·rcon(SB), R4
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LVX (R4), ESPERMW
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#endif
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MOVD $·rcon+0x10(SB), R4
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LOAD_CONSTS(R4, R3)
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MOVD xk+0(FP), rk
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MOVD dst+8(FP), dstPtr
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MOVD src+32(FP), srcPtr
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MOVD src_len+40(FP), srcLen
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MOVD $16, R7
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MOVD $32, R8
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MOVD $48, R10
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MOVD $64, R11
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MOVD $80, R12
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MOVD $96, R14
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MOVD $112, R15
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CMP srcLen, $128
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BLT block64
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preloop128:
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SRD $7, srcLen, R9 // Set up loop counter
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MOVD R9, CTR
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ANDCC $127, srcLen, R9 // Check for tailing bytes for later
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PCALIGN $16
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block128:
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// Case for >= 128 bytes
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PPC64X_LXVW4X(srcPtr, R0, V0)
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PPC64X_LXVW4X(srcPtr, R7, V1)
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PPC64X_LXVW4X(srcPtr, R8, V2)
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PPC64X_LXVW4X(srcPtr, R10, V3)
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PPC64X_LXVW4X(srcPtr, R11, V4)
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PPC64X_LXVW4X(srcPtr, R12, V5)
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PPC64X_LXVW4X(srcPtr, R14, V6)
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PPC64X_LXVW4X(srcPtr, R15, V7)
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PRE_TRANSPOSE_MATRIX(V0, V1, V2, V3)
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PRE_TRANSPOSE_MATRIX(V4, V5, V6, V7)
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LXVW4X (rk)(R0), V8
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PROCESS_8BLOCKS_4ROUND
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LXVW4X (rk)(R7), V8
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PROCESS_8BLOCKS_4ROUND
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LXVW4X (rk)(R8), V8
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PROCESS_8BLOCKS_4ROUND
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LXVW4X (rk)(R10), V8
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PROCESS_8BLOCKS_4ROUND
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LXVW4X (rk)(R11), V8
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PROCESS_8BLOCKS_4ROUND
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LXVW4X (rk)(R12), V8
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PROCESS_8BLOCKS_4ROUND
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LXVW4X (rk)(R14), V8
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PROCESS_8BLOCKS_4ROUND
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LXVW4X (rk)(R15), V8
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PROCESS_8BLOCKS_4ROUND
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TRANSPOSE_MATRIX(V0, V1, V2, V3)
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TRANSPOSE_MATRIX(V4, V5, V6, V7)
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PPC64X_STXVW4X(V0, dstPtr, R0)
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PPC64X_STXVW4X(V1, dstPtr, R7)
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PPC64X_STXVW4X(V2, dstPtr, R8)
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PPC64X_STXVW4X(V3, dstPtr, R10)
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PPC64X_STXVW4X(V4, dstPtr, R11)
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PPC64X_STXVW4X(V5, dstPtr, R12)
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PPC64X_STXVW4X(V6, dstPtr, R14)
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PPC64X_STXVW4X(V7, dstPtr, R15)
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ADD $128, srcPtr
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ADD $128, dstPtr
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BDNZ block128
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BC 12,2,LR // BEQLR, fast return
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MOVD R9, srcLen
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block64:
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CMP srcLen, $64
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BLT lessThan64
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PPC64X_LXVW4X(srcPtr, R0, V0)
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PPC64X_LXVW4X(srcPtr, R7, V1)
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PPC64X_LXVW4X(srcPtr, R8, V2)
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PPC64X_LXVW4X(srcPtr, R10, V3)
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PRE_TRANSPOSE_MATRIX(V0, V1, V2, V3)
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LXVW4X (rk)(R0), V8
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PROCESS_4BLOCKS_4ROUND
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LXVW4X (rk)(R7), V8
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PROCESS_4BLOCKS_4ROUND
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LXVW4X (rk)(R8), V8
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PROCESS_4BLOCKS_4ROUND
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LXVW4X (rk)(R10), V8
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PROCESS_4BLOCKS_4ROUND
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LXVW4X (rk)(R11), V8
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PROCESS_4BLOCKS_4ROUND
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LXVW4X (rk)(R12), V8
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PROCESS_4BLOCKS_4ROUND
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LXVW4X (rk)(R14), V8
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PROCESS_4BLOCKS_4ROUND
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LXVW4X (rk)(R15), V8
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PROCESS_4BLOCKS_4ROUND
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TRANSPOSE_MATRIX(V0, V1, V2, V3)
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PPC64X_STXVW4X(V0, dstPtr, R0)
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PPC64X_STXVW4X(V1, dstPtr, R7)
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PPC64X_STXVW4X(V2, dstPtr, R8)
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PPC64X_STXVW4X(V3, dstPtr, R10)
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ADD $64, srcPtr
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ADD $64, dstPtr
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ADD $-64, srcLen
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lessThan64:
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CMPU srcLen, $48, CR1
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CMPU srcLen, $32, CR2
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CMPU srcLen, $16, CR3
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BEQ CR1, block48
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BEQ CR2, block32
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BEQ CR3, block16
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RET
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block48:
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PPC64X_LXVW4X(srcPtr, R0, V0)
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PPC64X_LXVW4X(srcPtr, R7, V1)
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PPC64X_LXVW4X(srcPtr, R8, V2)
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PRE_TRANSPOSE_MATRIX(V0, V1, V2, V3)
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LXVW4X (rk)(R0), V8
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PROCESS_4BLOCKS_4ROUND
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LXVW4X (rk)(R7), V8
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PROCESS_4BLOCKS_4ROUND
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LXVW4X (rk)(R8), V8
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PROCESS_4BLOCKS_4ROUND
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LXVW4X (rk)(R10), V8
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PROCESS_4BLOCKS_4ROUND
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LXVW4X (rk)(R11), V8
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PROCESS_4BLOCKS_4ROUND
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LXVW4X (rk)(R12), V8
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PROCESS_4BLOCKS_4ROUND
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LXVW4X (rk)(R14), V8
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PROCESS_4BLOCKS_4ROUND
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LXVW4X (rk)(R15), V8
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PROCESS_4BLOCKS_4ROUND
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TRANSPOSE_MATRIX(V0, V1, V2, V3)
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PPC64X_STXVW4X(V0, dstPtr, R0)
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PPC64X_STXVW4X(V1, dstPtr, R7)
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PPC64X_STXVW4X(V2, dstPtr, R8)
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RET
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block32:
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PPC64X_LXVW4X(srcPtr, R0, V0)
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PPC64X_LXVW4X(srcPtr, R7, V1)
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PRE_TRANSPOSE_MATRIX(V0, V1, V2, V3)
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LXVW4X (rk)(R0), V8
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PROCESS_4BLOCKS_4ROUND
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LXVW4X (rk)(R7), V8
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PROCESS_4BLOCKS_4ROUND
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LXVW4X (rk)(R8), V8
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PROCESS_4BLOCKS_4ROUND
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LXVW4X (rk)(R10), V8
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PROCESS_4BLOCKS_4ROUND
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LXVW4X (rk)(R11), V8
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PROCESS_4BLOCKS_4ROUND
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LXVW4X (rk)(R12), V8
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PROCESS_4BLOCKS_4ROUND
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LXVW4X (rk)(R14), V8
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PROCESS_4BLOCKS_4ROUND
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LXVW4X (rk)(R15), V8
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PROCESS_4BLOCKS_4ROUND
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TRANSPOSE_MATRIX(V0, V1, V2, V3)
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PPC64X_STXVW4X(V0, dstPtr, R0)
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PPC64X_STXVW4X(V1, dstPtr, R7)
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RET
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block16:
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PPC64X_LXVW4X(srcPtr, R0, V0)
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VSLDOI $4, V0, V0, V1
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VSLDOI $4, V1, V1, V2
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VSLDOI $4, V2, V2, V3
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LXVW4X (rk)(R0), V8
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PROCESS_SINGLEBLOCK_4ROUND
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LXVW4X (rk)(R7), V8
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PROCESS_SINGLEBLOCK_4ROUND
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LXVW4X (rk)(R8), V8
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PROCESS_SINGLEBLOCK_4ROUND
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LXVW4X (rk)(R10), V8
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PROCESS_SINGLEBLOCK_4ROUND
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LXVW4X (rk)(R11), V8
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PROCESS_SINGLEBLOCK_4ROUND
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LXVW4X (rk)(R12), V8
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PROCESS_SINGLEBLOCK_4ROUND
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LXVW4X (rk)(R14), V8
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PROCESS_SINGLEBLOCK_4ROUND
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LXVW4X (rk)(R15), V8
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PROCESS_SINGLEBLOCK_4ROUND
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VSLDOI $4, V3, V3, V3
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VSLDOI $4, V3, V2, V2
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VSLDOI $4, V2, V1, V1
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VSLDOI $4, V1, V0, V0
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PPC64X_STXVW4X(V0, dstPtr, R0)
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RET
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