mirror of
https://github.com/emmansun/gmsm.git
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338 lines
7.0 KiB
ArmAsm
338 lines
7.0 KiB
ArmAsm
// Copyright 2024 Sun Yimin. All rights reserved.
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// Use of this source code is governed by a MIT-style
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// license that can be found in the LICENSE file.
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//go:build (ppc64 || ppc64le) && !purego
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#include "textflag.h"
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#define REVERSE_WORDS V19
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#define M1L V20
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#define M1H V21
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#define M2L V22
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#define M2H V23
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#define V_FOUR V24
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#define M0 V25
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#define M1 V26
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#define M2 V27
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#define M3 V28
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#define NIBBLE_MASK V29
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#define INVERSE_SHIFT_ROWS V30
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// For instruction emulation
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#define ESPERMW V31 // Endian swapping permute into BE
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#define TMP0 V10
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#define TMP1 V11
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#define TMP2 V12
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#define TMP3 V13
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#define IV V18
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#include "aesni_macros_ppc64x.s"
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#ifdef NEEDS_PERMW
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#define REVERSE32LE_8BLOCKS \
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VPERM V0, V0, ESPERMW, V0 \
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VPERM V1, V1, ESPERMW, V1 \
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VPERM V2, V2, ESPERMW, V2 \
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VPERM V3, V3, ESPERMW, V3 \
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VPERM V4, V4, ESPERMW, V4 \
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VPERM V5, V5, ESPERMW, V5 \
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VPERM V6, V6, ESPERMW, V6 \
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VPERM V7, V7, ESPERMW, V7
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#else
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#define REVERSE32LE_8BLOCKS
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#endif
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// func decryptBlocksChain(xk *uint32, dst, src []byte, iv *byte)
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TEXT ·decryptBlocksChain(SB),NOSPLIT,$0
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#define dstPtr R3
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#define srcPtr R4
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#define rk R5
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#define srcLen R6
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// prepare/load constants
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VSPLTISW $4, V_FOUR;
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#ifdef NEEDS_PERMW
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MOVD $·rcon(SB), R4
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LVX (R4), ESPERMW
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#endif
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MOVD $·rcon+0x10(SB), R4
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LOAD_CONSTS(R4, R3)
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// Load IV
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MOVD iv+56(FP), R7
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PPC64X_LXVW4X(R7, R0, IV)
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MOVD xk+0(FP), rk
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MOVD dst+8(FP), dstPtr
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MOVD src+32(FP), srcPtr
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MOVD src_len+40(FP), srcLen
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MOVD $16, R7
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MOVD $32, R8
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MOVD $48, R9
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MOVD $64, R10
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MOVD $80, R11
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MOVD $96, R12
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MOVD $112, R14
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ADD srcPtr, srcLen, R15
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ADD $-16, R15, R15
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LXVD2X (R15)(R0), V14 // Load last 16 bytes of src into V14
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CMP srcLen, $144 // 9 blocks
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BLT lessThan9blocks
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PCALIGN $16
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loop8blocks:
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ADD $-128, srcLen
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ADD srcPtr, srcLen, R15
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ADD $-16, R15, R16
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ADD dstPtr, srcLen, R17
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PPC64X_LXVW4X(R15, R0, V0)
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PPC64X_LXVW4X(R15, R7, V1)
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PPC64X_LXVW4X(R15, R8, V2)
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PPC64X_LXVW4X(R15, R9, V3)
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PPC64X_LXVW4X(R15, R10, V4)
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PPC64X_LXVW4X(R15, R11, V5)
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PPC64X_LXVW4X(R15, R12, V6)
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PPC64X_LXVW4X(R15, R14, V7)
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PRE_TRANSPOSE_MATRIX(V0, V1, V2, V3)
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PRE_TRANSPOSE_MATRIX(V4, V5, V6, V7)
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LXVW4X (rk)(R0), V8
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PROCESS_8BLOCKS_4ROUND
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LXVW4X (rk)(R7), V8
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PROCESS_8BLOCKS_4ROUND
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LXVW4X (rk)(R8), V8
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PROCESS_8BLOCKS_4ROUND
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LXVW4X (rk)(R9), V8
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PROCESS_8BLOCKS_4ROUND
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LXVW4X (rk)(R10), V8
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PROCESS_8BLOCKS_4ROUND
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LXVW4X (rk)(R11), V8
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PROCESS_8BLOCKS_4ROUND
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LXVW4X (rk)(R12), V8
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PROCESS_8BLOCKS_4ROUND
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LXVW4X (rk)(R14), V8
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PROCESS_8BLOCKS_4ROUND
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TRANSPOSE_MATRIX(V0, V1, V2, V3)
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TRANSPOSE_MATRIX(V4, V5, V6, V7)
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REVERSE32LE_8BLOCKS // for ppc64le
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LXVW4X (R16)(R0), TMP0
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LXVW4X (R16)(R7), TMP1
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LXVW4X (R16)(R8), TMP2
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LXVW4X (R16)(R9), TMP3
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VXOR V0, TMP0, V0
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VXOR V1, TMP1, V1
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VXOR V2, TMP2, V2
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VXOR V3, TMP3, V3
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LXVW4X (R16)(R10), TMP0
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LXVW4X (R16)(R11), TMP1
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LXVW4X (R16)(R12), TMP2
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LXVW4X (R16)(R14), TMP3
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VXOR V4, TMP0, V4
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VXOR V5, TMP1, V5
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VXOR V6, TMP2, V6
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VXOR V7, TMP3, V7
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STXVW4X V0, (R17)(R0)
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STXVW4X V1, (R17)(R7)
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STXVW4X V2, (R17)(R8)
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STXVW4X V3, (R17)(R9)
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STXVW4X V4, (R17)(R10)
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STXVW4X V5, (R17)(R11)
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STXVW4X V6, (R17)(R12)
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STXVW4X V7, (R17)(R14)
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CMP srcLen, $144 // 9 blocks
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BGE loop8blocks
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lessThan9blocks:
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CMP srcLen, $64
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BLE ble4blocks
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ADD $-64, srcLen
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ADD srcPtr, srcLen, R15
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ADD $-16, R15, R16
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ADD dstPtr, srcLen, R17
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PPC64X_LXVW4X(R15, R0, V0)
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PPC64X_LXVW4X(R15, R7, V1)
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PPC64X_LXVW4X(R15, R8, V2)
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PPC64X_LXVW4X(R15, R9, V3)
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VOR V0, V0, V5
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VOR V1, V1, V6
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VOR V2, V2, V7
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PRE_TRANSPOSE_MATRIX(V0, V1, V2, V3)
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LXVW4X (rk)(R0), V8
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PROCESS_4BLOCKS_4ROUND
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LXVW4X (rk)(R7), V8
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PROCESS_4BLOCKS_4ROUND
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LXVW4X (rk)(R8), V8
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PROCESS_4BLOCKS_4ROUND
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LXVW4X (rk)(R9), V8
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PROCESS_4BLOCKS_4ROUND
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LXVW4X (rk)(R10), V8
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PROCESS_4BLOCKS_4ROUND
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LXVW4X (rk)(R11), V8
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PROCESS_4BLOCKS_4ROUND
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LXVW4X (rk)(R12), V8
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PROCESS_4BLOCKS_4ROUND
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LXVW4X (rk)(R14), V8
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PROCESS_4BLOCKS_4ROUND
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TRANSPOSE_MATRIX(V0, V1, V2, V3)
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PPC64X_LXVW4X(R16, R0, V4)
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VXOR V0, V4, V0
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VXOR V1, V5, V1
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VXOR V2, V6, V2
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VXOR V3, V7, V3
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PPC64X_STXVW4X(V0, R17, R0)
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PPC64X_STXVW4X(V1, R17, R7)
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PPC64X_STXVW4X(V2, R17, R8)
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PPC64X_STXVW4X(V3, R17, R9)
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ble4blocks:
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CMPU srcLen, $48, CR1
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CMPU srcLen, $32, CR2
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CMPU srcLen, $16, CR3
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BEQ CR1, eq3blocks
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BEQ CR2, eq2blocks
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BEQ CR3, eq1block
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PPC64X_LXVW4X(srcPtr, R0, V0)
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PPC64X_LXVW4X(srcPtr, R7, V1)
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PPC64X_LXVW4X(srcPtr, R8, V2)
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PPC64X_LXVW4X(srcPtr, R9, V3)
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VOR V0, V0, V4
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VOR V1, V1, V5
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VOR V2, V2, V6
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PRE_TRANSPOSE_MATRIX(V0, V1, V2, V3)
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LXVW4X (rk)(R0), V8
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PROCESS_4BLOCKS_4ROUND
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LXVW4X (rk)(R7), V8
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PROCESS_4BLOCKS_4ROUND
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LXVW4X (rk)(R8), V8
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PROCESS_4BLOCKS_4ROUND
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LXVW4X (rk)(R9), V8
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PROCESS_4BLOCKS_4ROUND
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LXVW4X (rk)(R10), V8
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PROCESS_4BLOCKS_4ROUND
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LXVW4X (rk)(R11), V8
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PROCESS_4BLOCKS_4ROUND
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LXVW4X (rk)(R12), V8
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PROCESS_4BLOCKS_4ROUND
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LXVW4X (rk)(R14), V8
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PROCESS_4BLOCKS_4ROUND
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TRANSPOSE_MATRIX(V0, V1, V2, V3)
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VXOR V0, IV, V0
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VXOR V1, V4, V1
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VXOR V2, V5, V2
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VXOR V3, V6, V3
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PPC64X_STXVW4X(V0, dstPtr, R0)
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PPC64X_STXVW4X(V1, dstPtr, R7)
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PPC64X_STXVW4X(V2, dstPtr, R8)
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PPC64X_STXVW4X(V3, dstPtr, R9)
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BR done
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eq3blocks:
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PPC64X_LXVW4X(srcPtr, R0, V0)
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PPC64X_LXVW4X(srcPtr, R7, V1)
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PPC64X_LXVW4X(srcPtr, R8, V2)
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VOR V0, V0, V4
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VOR V1, V1, V5
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PRE_TRANSPOSE_MATRIX(V0, V1, V2, V3)
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LXVW4X (rk)(R0), V8
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PROCESS_4BLOCKS_4ROUND
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LXVW4X (rk)(R7), V8
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PROCESS_4BLOCKS_4ROUND
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LXVW4X (rk)(R8), V8
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PROCESS_4BLOCKS_4ROUND
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LXVW4X (rk)(R9), V8
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PROCESS_4BLOCKS_4ROUND
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LXVW4X (rk)(R10), V8
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PROCESS_4BLOCKS_4ROUND
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LXVW4X (rk)(R11), V8
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PROCESS_4BLOCKS_4ROUND
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LXVW4X (rk)(R12), V8
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PROCESS_4BLOCKS_4ROUND
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LXVW4X (rk)(R14), V8
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PROCESS_4BLOCKS_4ROUND
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TRANSPOSE_MATRIX(V0, V1, V2, V3)
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VXOR V0, IV, V0
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VXOR V1, V4, V1
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VXOR V2, V5, V2
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PPC64X_STXVW4X(V0, dstPtr, R0)
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PPC64X_STXVW4X(V1, dstPtr, R7)
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PPC64X_STXVW4X(V2, dstPtr, R8)
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BR done
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eq2blocks:
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PPC64X_LXVW4X(srcPtr, R0, V0)
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PPC64X_LXVW4X(srcPtr, R7, V1)
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VOR V0, V0, V4
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PRE_TRANSPOSE_MATRIX(V0, V1, V2, V3)
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LXVW4X (rk)(R0), V8
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PROCESS_4BLOCKS_4ROUND
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LXVW4X (rk)(R7), V8
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PROCESS_4BLOCKS_4ROUND
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LXVW4X (rk)(R8), V8
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PROCESS_4BLOCKS_4ROUND
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LXVW4X (rk)(R9), V8
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PROCESS_4BLOCKS_4ROUND
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LXVW4X (rk)(R10), V8
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PROCESS_4BLOCKS_4ROUND
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LXVW4X (rk)(R11), V8
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PROCESS_4BLOCKS_4ROUND
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LXVW4X (rk)(R12), V8
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PROCESS_4BLOCKS_4ROUND
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LXVW4X (rk)(R14), V8
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PROCESS_4BLOCKS_4ROUND
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TRANSPOSE_MATRIX(V0, V1, V2, V3)
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VXOR V0, IV, V0
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VXOR V1, V4, V1
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PPC64X_STXVW4X(V0, dstPtr, R0)
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PPC64X_STXVW4X(V1, dstPtr, R7)
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BR done
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eq1block:
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PPC64X_LXVW4X(srcPtr, R0, V0)
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VSLDOI $4, V0, V0, V1
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VSLDOI $4, V1, V1, V2
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VSLDOI $4, V2, V2, V3
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LXVW4X (rk)(R0), V8
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PROCESS_SINGLEBLOCK_4ROUND
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LXVW4X (rk)(R7), V8
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PROCESS_SINGLEBLOCK_4ROUND
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LXVW4X (rk)(R8), V8
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PROCESS_SINGLEBLOCK_4ROUND
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LXVW4X (rk)(R9), V8
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PROCESS_SINGLEBLOCK_4ROUND
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LXVW4X (rk)(R10), V8
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PROCESS_SINGLEBLOCK_4ROUND
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LXVW4X (rk)(R11), V8
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PROCESS_SINGLEBLOCK_4ROUND
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LXVW4X (rk)(R12), V8
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PROCESS_SINGLEBLOCK_4ROUND
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LXVW4X (rk)(R14), V8
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PROCESS_SINGLEBLOCK_4ROUND
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VSLDOI $4, V3, V3, V3
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VSLDOI $4, V3, V2, V2
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VSLDOI $4, V2, V1, V1
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VSLDOI $4, V1, V0, V0
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VXOR V0, IV, V0
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PPC64X_STXVW4X(V0, dstPtr, R0)
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done:
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MOVD iv+56(FP), R7
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STXVD2X V14, (R7)(R0)
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RET
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