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zuc: amd64 optimization step 1
This commit is contained in:
Sun Yimin
GitHub
parent
68f38a96af
commit
f7a55494c8
384
zuc/asm_amd64.s
Normal file
384
zuc/asm_amd64.s
Normal file
@ -0,0 +1,384 @@
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// Referenced https://github.com/intel/intel-ipsec-mb/
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//go:build amd64 && !generic
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// +build amd64,!generic
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#include "textflag.h"
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DATA Top3_bits_of_the_byte<>+0x00(SB)/8, $0xe0e0e0e0e0e0e0e0
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DATA Top3_bits_of_the_byte<>+0x08(SB)/8, $0xe0e0e0e0e0e0e0e0
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GLOBL Top3_bits_of_the_byte<>(SB), RODATA, $16
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DATA Bottom5_bits_of_the_byte<>+0x00(SB)/8, $0x1f1f1f1f1f1f1f1f
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DATA Bottom5_bits_of_the_byte<>+0x08(SB)/8, $0x1f1f1f1f1f1f1f1f
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GLOBL Bottom5_bits_of_the_byte<>(SB), RODATA, $16
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DATA Low_nibble_mask<>+0x00(SB)/8, $0x0F0F0F0F0F0F0F0F
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DATA Low_nibble_mask<>+0x08(SB)/8, $0x0F0F0F0F0F0F0F0F
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GLOBL Low_nibble_mask<>(SB), RODATA, $16
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DATA High_nibble_mask<>+0x00(SB)/8, $0xF0F0F0F0F0F0F0F0
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DATA High_nibble_mask<>+0x08(SB)/8, $0xF0F0F0F0F0F0F0F0
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GLOBL High_nibble_mask<>(SB), RODATA, $16
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DATA P1<>+0x00(SB)/8, $0x0A020F0F0E000F09
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DATA P1<>+0x08(SB)/8, $0x090305070C000400
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GLOBL P1<>(SB), RODATA, $16
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DATA P2<>+0x00(SB)/8, $0x040C000705060D08
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DATA P2<>+0x08(SB)/8, $0x0209030F0A0E010B
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GLOBL P2<>(SB), RODATA, $16
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DATA P3<>+0x00(SB)/8, $0x0F0A0D00060A0602
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DATA P3<>+0x08(SB)/8, $0x0D0C0900050D0303
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GLOBL P3<>(SB), RODATA, $16
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DATA Aes_to_Zuc_mul_low_nibble<>+0x00(SB)/8, $0x1D1C9F9E83820100
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DATA Aes_to_Zuc_mul_low_nibble<>+0x08(SB)/8, $0x3938BBBAA7A62524
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GLOBL Aes_to_Zuc_mul_low_nibble<>(SB), RODATA, $16
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DATA Aes_to_Zuc_mul_high_nibble<>+0x00(SB)/8, $0xA174A97CDD08D500
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DATA Aes_to_Zuc_mul_high_nibble<>+0x08(SB)/8, $0x3DE835E04194499C
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GLOBL Aes_to_Zuc_mul_high_nibble<>(SB), RODATA, $16
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DATA Comb_matrix_mul_low_nibble<>+0x00(SB)/8, $0x9A8E3024EBFF4155
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DATA Comb_matrix_mul_low_nibble<>+0x08(SB)/8, $0x2D3987935C48F6E2
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GLOBL Comb_matrix_mul_low_nibble<>(SB), RODATA, $16
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DATA Comb_matrix_mul_high_nibble<>+0x00(SB)/8, $0x638CFA1523CCBA55
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DATA Comb_matrix_mul_high_nibble<>+0x08(SB)/8, $0x3FD0A6497F90E609
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GLOBL Comb_matrix_mul_high_nibble<>(SB), RODATA, $16
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DATA Shuf_mask<>+0x00(SB)/8, $0x0B0E0104070A0D00
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DATA Shuf_mask<>+0x08(SB)/8, $0x0306090C0F020508
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GLOBL Shuf_mask<>(SB), RODATA, $16
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DATA Cancel_aes<>+0x00(SB)/8, $0x6363636363636363
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DATA Cancel_aes<>+0x08(SB)/8, $0x6363636363636363
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GLOBL Cancel_aes<>(SB), RODATA, $16
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DATA Const_comb_matrix<>+0x00(SB)/8, $0x5555555555555555
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DATA Const_comb_matrix<>+0x08(SB)/8, $0x5555555555555555
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GLOBL Const_comb_matrix<>(SB), RODATA, $16
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DATA CombMatrix<>+0x00(SB)/8, $0x3C1A99B2AD1ED43A
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DATA CombMatrix<>+0x08(SB)/8, $0x3C1A99B2AD1ED43A
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GLOBL CombMatrix<>(SB), RODATA, $16
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DATA mask_S0<>+0x00(SB)/8, $0xff00ff00ff00ff00
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DATA mask_S0<>+0x08(SB)/8, $0xff00ff00ff00ff00
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GLOBL mask_S0<>(SB), RODATA, $16
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DATA mask_S1<>+0x00(SB)/8, $0x00ff00ff00ff00ff
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DATA mask_S1<>+0x08(SB)/8, $0x00ff00ff00ff00ff
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GLOBL mask_S1<>(SB), RODATA, $16
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#define OFFSET_FR1 (16*4)
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#define OFFSET_FR2 (17*4)
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#define OFFSET_BRC_X0 (18*4)
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#define OFFSET_BRC_X1 (19*4)
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#define OFFSET_BRC_X2 (20*4)
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#define OFFSET_BRC_X3 (21*4)
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#define SHLDL(a, b, n) \ // NO SHLDL in GOLANG now
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SHLL n, a \
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SHRL n, b \
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ORL b, a
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#define Rotl_5_SSE(XDATA, XTMP0) \
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MOVOU XDATA, XTMP0 \
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PSLLQ $5, XTMP0 \ // should use pslld
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PSRLQ $3, XDATA \ // should use psrld
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PAND Top3_bits_of_the_byte<>(SB), XTMP0 \
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PAND Bottom5_bits_of_the_byte<>(SB), XDATA \
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POR XTMP0, XDATA
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#define S0_comput_SSE(IN_OUT, XTMP1, XTMP2) \
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MOVOU IN_OUT, XTMP1 \
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\
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PAND Low_nibble_mask<>(SB), IN_OUT \
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\
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PAND High_nibble_mask<>(SB), XTMP1 \
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PSRLQ $4, XTMP1 \
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\
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MOVOU P1<>(SB), XTMP2 \
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PSHUFB IN_OUT, XTMP2 \
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PXOR XTMP1, XTMP2 \
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\
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MOVOU P2<>(SB), XTMP1 \
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PSHUFB XTMP2, XTMP1 \
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PXOR IN_OUT, XTMP1 \
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\
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MOVOU P3<>(SB), IN_OUT \
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PSHUFB XTMP1, IN_OUT \
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PXOR XTMP2, IN_OUT \
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\
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PSLLQ $4, IN_OUT \
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POR XTMP1, IN_OUT \
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Rotl_5_SSE(IN_OUT, XTMP1)
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// Perform 8x8 matrix multiplication using lookup tables with partial results
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// for high and low nible of each input byte
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#define MUL_PSHUFB_SSE(XIN, XLO, XHI_OUT, XTMP) \
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MOVOU Low_nibble_mask<>(SB), XTMP \
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PAND XIN, XTMP \
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\
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PSHUFB XTMP, XLO \
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\
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MOVOU High_nibble_mask<>(SB), XTMP \
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PAND XIN, XTMP \
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PSRLQ $4, XTMP \
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\
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PSHUFB XTMP, XHI_OUT \
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\
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PXOR XLO, XHI_OUT
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// Compute 16 S1 box values from 16 bytes, stored in XMM register
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#define S1_comput_SSE(XIN_OUT, XTMP1, XTMP2, XTMP3) \
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MOVOU Aes_to_Zuc_mul_low_nibble<>(SB), XTMP1 \
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MOVOU Aes_to_Zuc_mul_high_nibble<>(SB), XTMP2 \
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MUL_PSHUFB_SSE(XIN_OUT, XTMP1, XTMP2, XTMP3) \
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\
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PSHUFB Shuf_mask<>(SB), XTMP2 \
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AESENCLAST Cancel_aes<>(SB), XTMP2 \
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\
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MOVOU Comb_matrix_mul_low_nibble<>(SB), XTMP1 \
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MOVOU Comb_matrix_mul_high_nibble<>(SB), XIN_OUT \
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MUL_PSHUFB_SSE(XTMP2, XTMP1, XIN_OUT, XTMP3) \
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PXOR Const_comb_matrix<>(SB), XIN_OUT
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#define Rotl_5_AVX(XDATA, XTMP0) \
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VPSLLD $5, XDATA, XTMP0 \
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VPSRLD $3, XDATA, XDATA \
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VPAND Top3_bits_of_the_byte<>(SB), XTMP0, XTMP0 \
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VPAND Bottom5_bits_of_the_byte<>(SB), XDATA, XDATA \
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VPOR XTMP0, XDATA, XDATA
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#define S0_comput_AVX(IN_OUT, XTMP1, XTMP2) \
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VPAND High_nibble_mask<>(SB), IN_OUT, XTMP1 \
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VPSRLQ $4, XTMP1, XTMP1 \
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\
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VPAND Low_nibble_mask<>(SB), IN_OUT, IN_OUT \
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\
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VMOVDQU P1<>(SB), XTMP2 \
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VPSHUFB IN_OUT, XTMP2, XTMP2 \
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VPXOR XTMP1, XTMP2, XTMP2 \
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\
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VMOVDQU P2<>(SB), XTMP1 \
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VPSHUFB XTMP2, XTMP1, XTMP1 \
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VPXOR IN_OUT, XTMP1, XTMP1 \
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\
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VMOVDQU P3<>(SB), IN_OUT \
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VPSHUFB XTMP1, IN_OUT, IN_OUT \
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VPXOR XTMP2, IN_OUT, IN_OUT \
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\
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VPSLLQ $4, IN_OUT, IN_OUT \
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VPOR XTMP1, IN_OUT, IN_OUT \
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Rotl_5_AVX(IN_OUT, XTMP1)
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// Perform 8x8 matrix multiplication using lookup tables with partial results
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// for high and low nible of each input byte
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#define MUL_PSHUFB_AVX(XIN, XLO, XHI_OUT, XTMP) \
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VPAND Low_nibble_mask<>(SB), XIN, XTMP \
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VPSHUFB XTMP, XLO, XLO \
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VPAND High_nibble_mask<>(SB), XIN, XTMP \
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VPSRLQ $4, XTMP, XTMP \
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VPSHUFB XTMP, XHI_OUT, XHI_OUT \
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VPXOR XLO, XHI_OUT, XHI_OUT
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// Compute 16 S1 box values from 16 bytes, stored in XMM register
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#define S1_comput_AVX(XIN_OUT, XTMP1, XTMP2, XTMP3) \
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VMOVDQU Aes_to_Zuc_mul_low_nibble<>(SB), XTMP1 \
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VMOVDQU Aes_to_Zuc_mul_high_nibble<>(SB), XTMP2 \
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MUL_PSHUFB_AVX(XIN_OUT, XTMP1, XTMP2, XTMP3) \
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VPSHUFB Shuf_mask<>(SB), XTMP2, XTMP2 \
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VAESENCLAST Cancel_aes<>(SB), XTMP2, XTMP2 \
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VMOVDQU Comb_matrix_mul_low_nibble<>(SB), XTMP1 \
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VMOVDQU Comb_matrix_mul_high_nibble<>(SB), XIN_OUT \
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MUL_PSHUFB_AVX(XTMP2, XTMP1, XIN_OUT, XTMP3) \
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VPXOR Const_comb_matrix<>(SB), XIN_OUT, XIN_OUT
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// BITS_REORG(idx)
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// params
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// %1 - round number
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// uses
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// AX, BX, CX, DX
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// return
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// R12, R13, R14, R15
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#define BITS_REORG(idx) \
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MOVL (((15 + idx) % 16)*4)(SI), R12 \
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MOVL (((14 + idx) % 16)*4)(SI), AX \
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MOVL (((11 + idx) % 16)*4)(SI), R13 \
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MOVL (((9 + idx) % 16)*4)(SI), BX \
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MOVL (((7 + idx) % 16)*4)(SI), R14 \
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MOVL (((5 + idx) % 16)*4)(SI), CX \
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MOVL (((2 + idx) % 16)*4)(SI), R15 \
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MOVL (((0 + idx) % 16)*4)(SI), DX \
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SHRL $15, R12 \
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SHLL $16, AX \
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SHLL $1, BX \
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SHLL $1, CX \
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SHLL $1, DX \
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SHLDL(R12, AX, $16) \
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SHLDL(R13, BX, $16) \
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SHLDL(R14, CX, $16) \
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SHLDL(R15, DX, $16)
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#define LFSR_UPDT(idx) \
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MOVL (((0 + idx) % 16)*4)(SI), BX \
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MOVL (((4 + idx) % 16)*4)(SI), CX \
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MOVL (((10 + idx) % 16)*4)(SI), DX \
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MOVL (((13 + idx) % 16)*4)(SI), R8 \
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MOVL (((15 + idx) % 16)*4)(SI), R9 \
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ADDQ BX, AX \
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SHLQ $8, BX \
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SHLQ $20, CX \
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SHLQ $21, DX \
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SHLQ $17, R8 \
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SHLQ $15, R9 \
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ADDQ BX, AX \
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ADDQ CX, AX \
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ADDQ DX, AX \
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ADDQ R8, AX \
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ADDQ R9, AX \
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\
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MOVQ AX, BX \
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ANDQ $0x7FFFFFFF, AX \
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SHRQ $31, BX \
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ADDQ BX, AX \
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\
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MOVQ AX, BX \
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SUBQ $0x7FFFFFFF, AX \
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CMOVQCS BX, AX \
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\
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MOVL AX, (((0 + idx) % 16)*4)(SI)
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#define NONLIN_FUN() \
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MOVL R12, AX \
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XORL R10, AX \
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ADDL R11, AX \
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ADDL R13, R10 \ // W1= F_R1 + BRC_X1
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XORL R14, R11 \ // W2= F_R2 ^ BRC_X2
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\
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MOVL R10, DX \
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MOVL R11, CX \
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SHLDL(DX, CX, $16) \ // P = (W1 << 16) | (W2 >> 16)
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SHLDL(R11, R10, $16) \ // Q = (W2 << 16) | (W1 >> 16)
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MOVL DX, BX \
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MOVL DX, CX \
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MOVL DX, R8 \
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MOVL DX, R9 \
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ROLL $2, BX \
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ROLL $10, CX \
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ROLL $18, R8 \
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ROLL $24, R9 \
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XORL BX, DX \
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XORL CX, DX \
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XORL R8, DX \
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XORL R9, DX \ // U = L1(P) = EDX, hi(RDX)=0
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MOVL R11, BX \
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MOVL R11, CX \
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MOVL R11, R8 \
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MOVL R11, R9 \
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ROLL $8, BX \
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ROLL $14, CX \
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ROLL $22, R8 \
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ROLL $30, R9 \
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XORL BX, R11 \
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XORL CX, R11 \
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XORL R8, R11 \
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XORL R9, R11 \ // V = L2(Q) = R11D, hi(R11)=0
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SHLQ $32, R11 \
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XORQ R11, DX
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#define NONLIN_FUN_SSE() \
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NONLIN_FUN() \
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MOVQ DX, X0 \
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MOVOU X0, X1 \
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S0_comput_SSE(X1, X2, X3) \
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S1_comput_SSE(X0, X2, X3, X4) \
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\
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PAND mask_S1<>(SB), X0 \
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PAND mask_S0<>(SB), X1 \
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PXOR X1, X0 \
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\
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MOVL X0, R10 \ // F_R1
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PEXTRD $1, X0, R11
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#define RESTORE_LFSR_0() \
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MOVL (0*4)(SI), AX \
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MOVUPS (4)(SI), X0 \
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MOVUPS (20)(SI), X1 \
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MOVUPS (36)(SI), X2 \
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MOVQ (52)(SI), BX \
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MOVL (60)(SI), CX \
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MOVUPS X0, (SI) \
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MOVUPS X1, (16)(SI) \
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MOVUPS X2, (32)(SI) \
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MOVQ BX, (48)(SI) \
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MOVL CX, (56)(SI) \
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MOVL AX, (60)(SI)
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#define NONLIN_FUN_AVX() \
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NONLIN_FUN() \
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VMOVQ DX, X0 \
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VMOVDQA X0, X1 \
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S0_comput_AVX(X1, X2, X3) \
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S1_comput_AVX(X0, X2, X3, X4) \
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\
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VPAND mask_S1<>(SB), X0, X0 \
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VPAND mask_S0<>(SB), X1, X1 \
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VPXOR X1, X0, X0 \
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\
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MOVL X0, R10 \ // F_R1
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VPEXTRD $1, X0, R11
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#define SAVE_STATE() \
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MOVL R10, OFFSET_FR1(SI) \
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MOVL R11, OFFSET_FR2(SI) \
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MOVL R12, OFFSET_BRC_X0(SI) \
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MOVL R13, OFFSET_BRC_X1(SI) \
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MOVL R14, OFFSET_BRC_X2(SI) \
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MOVL R15, OFFSET_BRC_X3(SI)
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// func genKeywordAsm(s *zucState32) uint32
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TEXT ·genKeywordAsm(SB),NOSPLIT,$0
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MOVQ pState+0(FP), SI
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MOVL OFFSET_FR1(SI), R10
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MOVL OFFSET_FR2(SI), R11
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MOVL OFFSET_BRC_X0(SI), R12
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MOVL OFFSET_BRC_X1(SI), R13
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MOVL OFFSET_BRC_X2(SI), R14
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MOVL OFFSET_BRC_X3(SI), R15
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BITS_REORG(0)
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CMPB ·useAVX(SB), $1
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JE avx
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sse:
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NONLIN_FUN_SSE()
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XORL R15, AX
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MOVL AX, ret+8(FP)
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XORQ AX, AX
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LFSR_UPDT(0)
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SAVE_STATE()
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RESTORE_LFSR_0()
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RET
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avx:
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NONLIN_FUN_AVX()
|
||||
|
||||
XORL R15, AX
|
||||
MOVL AX, ret+8(FP)
|
||||
XORQ AX, AX
|
||||
LFSR_UPDT(0)
|
||||
SAVE_STATE()
|
||||
RESTORE_LFSR_0()
|
||||
|
||||
VZEROUPPER
|
||||
RET
|
||||
@ -219,17 +219,12 @@ func newZUCState(key, iv []byte) (*zucState32, error) {
|
||||
}
|
||||
|
||||
func (s *zucState32) genKeyword() uint32 {
|
||||
s.bitReorganization()
|
||||
z := s.x3 ^ s.f32()
|
||||
s.enterWorkMode()
|
||||
return z
|
||||
return genKeyword(s)
|
||||
}
|
||||
|
||||
func (s *zucState32) genKeywords(words []uint32) {
|
||||
if len(words) == 0 {
|
||||
return
|
||||
}
|
||||
for i := 0; i < len(words); i++ {
|
||||
words[i] = s.genKeyword()
|
||||
}
|
||||
genKeyStream(words, s)
|
||||
}
|
||||
|
||||
31
zuc/core_asm.go
Normal file
31
zuc/core_asm.go
Normal file
@ -0,0 +1,31 @@
|
||||
//go:build (amd64 && !generic)
|
||||
// +build amd64,!generic
|
||||
|
||||
package zuc
|
||||
|
||||
import (
|
||||
"golang.org/x/sys/cpu"
|
||||
)
|
||||
|
||||
var supportsAES = cpu.X86.HasAES
|
||||
var useAVX = cpu.X86.HasAVX
|
||||
|
||||
//go:noescape
|
||||
func genKeywordAsm(s *zucState32) uint32
|
||||
|
||||
func genKeyStream(keyStream []uint32, pState *zucState32) {
|
||||
// TODO: will change the implementation later
|
||||
for i := 0; i < len(keyStream); i++ {
|
||||
keyStream[i] = genKeyword(pState)
|
||||
}
|
||||
}
|
||||
|
||||
func genKeyword(s *zucState32) uint32 {
|
||||
if supportsAES {
|
||||
return genKeywordAsm(s)
|
||||
}
|
||||
s.bitReorganization()
|
||||
z := s.x3 ^ s.f32()
|
||||
s.enterWorkMode()
|
||||
return z
|
||||
}
|
||||
17
zuc/core_generic.go
Normal file
17
zuc/core_generic.go
Normal file
@ -0,0 +1,17 @@
|
||||
//go:build !amd64 || generic
|
||||
// +build !amd64 generic
|
||||
|
||||
package zuc
|
||||
|
||||
func genKeyStream(keyStream []uint32, pState *zucState32) {
|
||||
for i := 0; i < len(keyStream); i++ {
|
||||
keyStream[i] = pState.genKeyword()
|
||||
}
|
||||
}
|
||||
|
||||
func genKeyword(s *zucState32) uint32 {
|
||||
s.bitReorganization()
|
||||
z := s.x3 ^ s.f32()
|
||||
s.enterWorkMode()
|
||||
return z
|
||||
}
|
||||
Loading…
x
Reference in New Issue
Block a user