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https://github.com/emmansun/gmsm.git
synced 2025-04-26 12:16:20 +08:00
fix sm3 arm64 instruction issue
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Emman
parent
38d90d45c7
commit
c4a96144da
@ -7,48 +7,50 @@
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#define BX R4
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#define CX R5
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#define DX R6
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#define hlp0 R9
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#define hlp1 R10
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// Wt = Mt; for 0 <= t <= 3
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#define MSGSCHEDULE0(index) \
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MOVWU (index*4)(SI), AX; \
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MOVW (index*4)(SI), AX; \
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REVW AX; \
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MOVWU AX, (index*4)(BP)
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MOVW AX, (index*4)(BP)
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// Wt+4 = Mt+4; for 0 <= t <= 11
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#define MSGSCHEDULE01(index) \
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MOVWU ((index+4)*4)(SI), AX; \
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MOVW ((index+4)*4)(SI), AX; \
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REVW AX; \
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MOVWU AX, ((index+4)*4)(BP)
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MOVW AX, ((index+4)*4)(BP)
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// x = Wt-12 XOR Wt-5 XOR ROTL(15, Wt+1)
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// p1(x) = x XOR ROTL(15, x) XOR ROTL(23, x)
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// Wt+4 = p1(x) XOR ROTL(7, Wt-9) XOR Wt-2
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// for 12 <= t <= 63
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#define MSGSCHEDULE1(index) \
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MOVWU ((index+1)*4)(BP), AX; \
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MOVW ((index+1)*4)(BP), AX; \
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RORW $17, AX; \
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MOVWU ((index-12)*4)(BP), BX; \
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MOVW ((index-12)*4)(BP), BX; \
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EORW BX, AX; \
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MOVWU ((index-5)*4)(BP), BX; \
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MOVW ((index-5)*4)(BP), BX; \
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EORW BX, AX; \
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MOVWU AX, BX; \
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MOVW AX, BX; \
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RORW $17, BX; \
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MOVWU AX, CX; \
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MOVW AX, CX; \
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RORW $9, CX; \
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EORW BX, AX; \
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EORW CX, AX; \
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MOVWU ((index-9)*4)(BP), BX; \
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MOVW ((index-9)*4)(BP), BX; \
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RORW $25, BX; \
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MOVWU ((index-2)*4)(BP), CX; \
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MOVW ((index-2)*4)(BP), CX; \
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EORW BX, AX; \
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EORW CX, AX; \
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MOVWU AX, ((index+4)*4)(BP)
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MOVW AX, ((index+4)*4)(BP)
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// Calculate ss1 in BX
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// x = ROTL(12, a) + e + ROTL(index, const)
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// ret = ROTL(7, x)
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#define SM3SS1(const, a, e) \
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MOVWU a, BX; \
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MOVW a, BX; \
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RORW $20, BX; \
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ADDW e, BX; \
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ADDW $const, BX; \
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@ -57,14 +59,14 @@
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// Calculate tt1 in CX
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// ret = (a XOR b XOR c) + d + (ROTL(12, a) XOR ss1) + (Wt XOR Wt+4)
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#define SM3TT10(index, a, b, c, d) \
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MOVWU a, CX; \
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MOVWU b, DX; \
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MOVW a, CX; \
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MOVW b, DX; \
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EORW CX, DX; \
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MOVWU c, DI; \
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EORW DI, DX; \ // (a XOR b XOR c)
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MOVW c, hlp0; \
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EORW hlp0, DX; \ // (a XOR b XOR c)
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ADDW d, DX; \ // (a XOR b XOR c) + d
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MOVWU ((index)*4)(BP), DI; \ //Wt
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EORW DI, AX; \ //Wt XOR Wt+4
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MOVW ((index)*4)(BP), hlp0; \ //Wt
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EORW hlp0, AX; \ //Wt XOR Wt+4
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ADDW AX, DX; \
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RORW $20, CX; \
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EORW BX, CX; \ // ROTL(12, a) XOR ss1
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@ -73,60 +75,60 @@
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// Calculate tt2 in BX
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// ret = (e XOR f XOR g) + h + ss1 + Wt
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#define SM3TT20(e, f, g, h) \
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ADDW h, DI; \ //Wt + h
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ADDW BX, DI; \ //Wt + h + ss1
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MOVWU e, BX; \
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MOVWU f, DX; \
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ADDW h, hlp0; \ //Wt + h
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ADDW BX, hlp0; \ //Wt + h + ss1
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MOVW e, BX; \
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MOVW f, DX; \
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EORW DX, BX; \ // e XOR f
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MOVWU g, DX; \
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MOVW g, DX; \
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EORW DX, BX; \ // e XOR f XOR g
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ADDW DI, BX // (e XOR f XOR g) + Wt + h + ss1
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ADDW hlp0, BX // (e XOR f XOR g) + Wt + h + ss1
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// Calculate tt1 in CX, used DX, DI
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// Calculate tt1 in CX, used DX, hlp0
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// ret = ((a AND b) OR (a AND c) OR (b AND c)) + d + (ROTL(12, a) XOR ss1) + (Wt XOR Wt+4)
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#define SM3TT11(index, a, b, c, d) \
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MOVWU a, CX; \
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MOVWU b, DX; \
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MOVW a, CX; \
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MOVW b, DX; \
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ANDW CX, DX; \ // a AND b
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MOVWU c, DI; \
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ANDW DI, CX; \ // a AND c
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MOVW c, hlp0; \
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ANDW hlp0, CX; \ // a AND c
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ORRW DX, CX; \ // (a AND b) OR (a AND c)
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MOVWU b, DX; \
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ANDW DI, DX; \ // b AND c
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MOVW b, DX; \
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ANDW hlp0, DX; \ // b AND c
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ORRW CX, DX; \ // (a AND b) OR (a AND c) OR (b AND c)
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ADDW d, DX; \
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MOVWU a, CX; \
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MOVW a, CX; \
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RORW $20, CX; \
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EORW BX, CX; \
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ADDW DX, CX; \ // ((a AND b) OR (a AND c) OR (b AND c)) + d + (ROTL(12, a) XOR ss1)
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MOVWU ((index)*4)(BP), DI; \
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EORW DI, AX; \ // Wt XOR Wt+4
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MOVW ((index)*4)(BP), hlp0; \
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EORW hlp0, AX; \ // Wt XOR Wt+4
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ADDW AX, CX
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// Calculate tt2 in BX
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// ret = ((e AND f) OR (NOT(e) AND g)) + h + ss1 + Wt
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#define SM3TT21(e, f, g, h) \
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ADDW h, DI; \ // Wt + h
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ADDW BX, DI; \ // h + ss1 + Wt
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MOVWU e, BX; \
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MOVWU f, DX; \
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ADDW h, hlp0; \ // Wt + h
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ADDW BX, hlp0; \ // h + ss1 + Wt
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MOVW e, BX; \
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MOVW f, DX; \
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ANDW BX, DX; \ // e AND f
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NOTL BX; \ // NOT(e)
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MOVWU g, AX; \
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MVNW BX, BX; \ // NOT(e)
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MOVW g, AX; \
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ANDW AX, BX; \ // NOT(e) AND g
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ORRW DX, BX; \
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ADDW DI, BX
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ADDW hlp0, BX
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#define COPYRESULT(b, d, f, h) \
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RORW $23, b; \
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MOVWU CX, h; \ // a = ttl
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MOVW CX, h; \ // a = ttl
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RORW $13, f; \
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MOVWU BX, CX; \
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MOVW BX, CX; \
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RORW $23, CX; \
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EORW BX, CX; \ // tt2 XOR ROTL(9, tt2)
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RORW $15, BX; \
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EORW BX, CX; \ // tt2 XOR ROTL(9, tt2) XOR ROTL(17, tt2)
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MOVWU CX, d // e = tt2 XOR ROTL(9, tt2) XOR ROTL(17, tt2)
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MOVW CX, d // e = tt2 XOR ROTL(9, tt2) XOR ROTL(17, tt2)
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#define SM3ROUND0(index, const, a, b, c, d, e, f, g, h) \
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MSGSCHEDULE01(index); \
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@ -151,29 +153,22 @@
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// func block(dig *digest, p []byte)
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TEXT ·block(SB), 0, $1048-32
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MOVD dig+0(FP), hlp1
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MOVD p_base+8(FP), SI
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MOVD p_len+16(FP), DX
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LSR $6, DX
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LSL $6, DX
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ADD DX, SI, DI
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MOVD DI, 272(RSP)
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CMP SI, DI
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BEQ end
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MOVD dig+0(FP), BP
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MOVWU (0*4)(BP), R19 // a = H0
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MOVWU (1*4)(BP), R20 // b = H1
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MOVWU (2*4)(BP), R21 // c = H2
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MOVWU (3*4)(BP), R22 // d = H3
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MOVWU (4*4)(BP), R23 // e = H4
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MOVWU (5*4)(BP), R24 // f = H5
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MOVWU (6*4)(BP), R25 // g = H6
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MOVWU (7*4)(BP), R26 // h = H7
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loop:
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MOVD RSP, BP
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AND $~63, DX
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CBZ DX, end
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ADD SI, DX, DI
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LDPW (0*8)(hlp1), (R19, R20)
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LDPW (1*8)(hlp1), (R21, R22)
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LDPW (2*8)(hlp1), (R23, R24)
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LDPW (3*8)(hlp1), (R25, R26)
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loop:
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MSGSCHEDULE0(0)
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MSGSCHEDULE0(1)
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MSGSCHEDULE0(2)
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@ -246,28 +241,25 @@ loop:
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SM3ROUND2(62, 0x9ea1e762, R21, R22, R23, R24, R25, R26, R19, R20)
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SM3ROUND2(63, 0x3d43cec5, R20, R21, R22, R23, R24, R25, R26, R19)
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MOVD dig+0(FP), BP
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EORW (0*4)(hlp1), R19 // H0 = a XOR H0
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EORW (1*4)(hlp1), R20 // H1 = b XOR H1
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STPW (R19, R20), (0*8)(hlp1)
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EORW (0*4)(BP), R19 // H0 = a XOR H0
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MOVWU R19, (0*4)(BP)
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EORW (1*4)(BP), R20 // H1 = b XOR H1
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MOVWU R20, (1*4)(BP)
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EORW (2*4)(BP), R21 // H2 = c XOR H2
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MOVWU R21, (2*4)(BP)
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EORW (3*4)(BP), R22 // H3 = d XOR H3
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MOVWU R22, (3*4)(BP)
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EORW (4*4)(BP), R23 // H4 = e XOR H4
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MOVWU R23, (4*4)(BP)
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EORW (5*4)(BP), R24 // H5 = f XOR H5
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MOVWU R24, (5*4)(BP)
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EORW (6*4)(BP), R25 // H6 = g XOR H6
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MOVWU R25, (6*4)(BP)
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EORW (7*4)(BP), R26 // H7 = h XOR H7
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MOVWU R26, (7*4)(BP)
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EORW (2*4)(hlp1), R21 // H2 = c XOR H2
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EORW (3*4)(hlp1), R22 // H3 = d XOR H3
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STPW (R21, R22), (1*8)(hlp1)
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EORW (4*4)(hlp1), R23 // H4 = e XOR H4
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EORW (5*4)(hlp1), R24 // H5 = f XOR H5
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STPW (R23, R24), (2*8)(hlp1)
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EORW (6*4)(hlp1), R25 // H6 = g XOR H6
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EORW (7*4)(hlp1), R26 // H7 = h XOR H7
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STPW (R25, R26), (3*8)(hlp1)
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ADD $64, SI
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CMP SI, 272(SP)
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BCC loop
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CMP SI, DI
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BNE loop
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end:
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RET
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