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sm4: ppc64x, use VSRD to replace VSRW

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Sun Yimin 2024-09-11 16:29:45 +08:00 committed by GitHub
parent 69d3481edc
commit 7cc5130380
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1 changed files with 5 additions and 4 deletions
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sm4/asm_ppc64x.s
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@ -89,7 +89,7 @@ GLOBL ·rcon(SB), RODATA, $192
#define AFFINE_TRANSFORM(L, H, V_FOUR, x, y, z) \ #define AFFINE_TRANSFORM(L, H, V_FOUR, x, y, z) \
VAND NIBBLE_MASK, x, z; \ VAND NIBBLE_MASK, x, z; \
VPERM L, L, z, y; \ VPERM L, L, z, y; \
VSRW x, V_FOUR, x; \ VSRD x, V_FOUR, x; \
VAND NIBBLE_MASK, x, z; \ VAND NIBBLE_MASK, x, z; \
VPERM H, H, z, x; \ VPERM H, H, z, x; \
VXOR y, x, x VXOR y, x, x
@ -101,10 +101,11 @@ GLOBL ·rcon(SB), RODATA, $192
// - x: 128 bits register as sbox input/output data // - x: 128 bits register as sbox input/output data
// - y: 128 bits temp register // - y: 128 bits temp register
// - z: 128 bits temp register // - z: 128 bits temp register
#define AFFINE_TRANSFORM_N(L, H, V_FOUR, x, y, z) \ #define AFFINE_TRANSFORM_NOTX(L, H, V_FOUR, x, y, z) \
VNAND NIBBLE_MASK, x, z; \ // VNAND is NOT same as AMD64 PANDN VNOR x, x, z; \
VAND NIBBLE_MASK, z, z; \
VPERM L, L, z, y; \ VPERM L, L, z, y; \
VSRW x, V_FOUR, x; \ VSRD x, V_FOUR, x; \
VAND NIBBLE_MASK, x, z; \ VAND NIBBLE_MASK, x, z; \
VPERM H, H, z, x; \ VPERM H, H, z, x; \
VXOR y, x, x VXOR y, x, x