adjust register

This commit is contained in:
Emman 2021-12-27 15:17:41 +08:00
parent a4081f8b2e
commit 663259b408

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@ -7,8 +7,8 @@
#define BX R4
#define CX R5
#define DX R6
#define hlp0 R9
#define hlp1 R10
#define hlp0 R7
#define hlp1 R9
// Wt = Mt; for 0 <= t <= 3
#define MSGSCHEDULE0(index) \