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sm4: code format
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Sun Yimin
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@ -20,7 +20,7 @@ DATA inverse_shift_rows<>+0x10(SB)/8, $0x0B0E0104070A0D00
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DATA inverse_shift_rows<>+0x18(SB)/8, $0x0306090C0F020508
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DATA inverse_shift_rows<>+0x18(SB)/8, $0x0306090C0F020508
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GLOBL inverse_shift_rows<>(SB), 8, $32
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GLOBL inverse_shift_rows<>(SB), 8, $32
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// Affine transform 1 (low and high hibbles)
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// Affine transform 1 (low and high nibbles)
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DATA m1_low<>+0x00(SB)/8, $0x0A7FC3B6D5A01C69
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DATA m1_low<>+0x00(SB)/8, $0x0A7FC3B6D5A01C69
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DATA m1_low<>+0x08(SB)/8, $0x3045F98CEF9A2653
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DATA m1_low<>+0x08(SB)/8, $0x3045F98CEF9A2653
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DATA m1_low<>+0x10(SB)/8, $0x0A7FC3B6D5A01C69
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DATA m1_low<>+0x10(SB)/8, $0x0A7FC3B6D5A01C69
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@ -33,7 +33,7 @@ DATA m1_high<>+0x10(SB)/8, $0xC35BF46CAF379800
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DATA m1_high<>+0x18(SB)/8, $0x68F05FC7049C33AB
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DATA m1_high<>+0x18(SB)/8, $0x68F05FC7049C33AB
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GLOBL m1_high<>(SB), 8, $32
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GLOBL m1_high<>(SB), 8, $32
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// Affine transform 2 (low and high hibbles)
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// Affine transform 2 (low and high nibbles)
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DATA m2_low<>+0x00(SB)/8, $0x9A950A05FEF16E61
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DATA m2_low<>+0x00(SB)/8, $0x9A950A05FEF16E61
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DATA m2_low<>+0x08(SB)/8, $0x0E019E916A65FAF5
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DATA m2_low<>+0x08(SB)/8, $0x0E019E916A65FAF5
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DATA m2_low<>+0x10(SB)/8, $0x9A950A05FEF16E61
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DATA m2_low<>+0x10(SB)/8, $0x9A950A05FEF16E61
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@ -270,10 +270,10 @@ GLOBL fk_mask<>(SB), 8, $16
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SM4_4BLOCKS_4ROUNDS(rk128, x, y, z, t0, t1, t2, t3); \
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SM4_4BLOCKS_4ROUNDS(rk128, x, y, z, t0, t1, t2, t3); \
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MOVOU (7*16)(RK), rk128; \
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MOVOU (7*16)(RK), rk128; \
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SM4_4BLOCKS_4ROUNDS(rk128, x, y, z, t0, t1, t2, t3); \
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SM4_4BLOCKS_4ROUNDS(rk128, x, y, z, t0, t1, t2, t3); \
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SSE_TRANSPOSE_MATRIX(t0, t1, t2, t3, x, y); \
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SSE_TRANSPOSE_MATRIX(t0, t1, t2, t3, x, y); \
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PSHUFB bswap_mask<>(SB), t3; \
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PSHUFB bswap_mask<>(SB), t3; \
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PSHUFB bswap_mask<>(SB), t2; \
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PSHUFB bswap_mask<>(SB), t2; \
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PSHUFB bswap_mask<>(SB), t1; \
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PSHUFB bswap_mask<>(SB), t1; \
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PSHUFB bswap_mask<>(SB), t0
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PSHUFB bswap_mask<>(SB), t0
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#define SM4_8BLOCKS_4ROUNDS(rk128, x, y, z, t0, t1, t2, t3, t4, t5, t6, t7) \
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#define SM4_8BLOCKS_4ROUNDS(rk128, x, y, z, t0, t1, t2, t3, t4, t5, t6, t7) \
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@ -306,33 +306,33 @@ GLOBL fk_mask<>(SB), 8, $16
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SM4_8BLOCKS_WO_BS(RK, rk128, x, y, z, t0, t1, t2, t3, t4, t5, t6, t7)
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SM4_8BLOCKS_WO_BS(RK, rk128, x, y, z, t0, t1, t2, t3, t4, t5, t6, t7)
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#define SM4_8BLOCKS_WO_BS(RK, rk128, x, y, z, t0, t1, t2, t3, t4, t5, t6, t7) \
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#define SM4_8BLOCKS_WO_BS(RK, rk128, x, y, z, t0, t1, t2, t3, t4, t5, t6, t7) \
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SSE_TRANSPOSE_MATRIX(t0, t1, t2, t3, x, y); \
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SSE_TRANSPOSE_MATRIX(t0, t1, t2, t3, x, y); \
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SSE_TRANSPOSE_MATRIX(t4, t5, t6, t7, x, y); \
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SSE_TRANSPOSE_MATRIX(t4, t5, t6, t7, x, y); \
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MOVOU (0*16)(RK), rk128; \
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MOVOU (0*16)(RK), rk128; \
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SM4_8BLOCKS_4ROUNDS(rk128, x, y, z, t0, t1, t2, t3, t4, t5, t6, t7); \
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SM4_8BLOCKS_4ROUNDS(rk128, x, y, z, t0, t1, t2, t3, t4, t5, t6, t7); \
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MOVOU (1*16)(RK), rk128; \
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MOVOU (1*16)(RK), rk128; \
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SM4_8BLOCKS_4ROUNDS(rk128, x, y, z, t0, t1, t2, t3, t4, t5, t6, t7); \
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SM4_8BLOCKS_4ROUNDS(rk128, x, y, z, t0, t1, t2, t3, t4, t5, t6, t7); \
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MOVOU (2*16)(RK), rk128; \
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MOVOU (2*16)(RK), rk128; \
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SM4_8BLOCKS_4ROUNDS(rk128, x, y, z, t0, t1, t2, t3, t4, t5, t6, t7); \
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SM4_8BLOCKS_4ROUNDS(rk128, x, y, z, t0, t1, t2, t3, t4, t5, t6, t7); \
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MOVOU (3*16)(RK), rk128; \
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MOVOU (3*16)(RK), rk128; \
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SM4_8BLOCKS_4ROUNDS(rk128, x, y, z, t0, t1, t2, t3, t4, t5, t6, t7); \
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SM4_8BLOCKS_4ROUNDS(rk128, x, y, z, t0, t1, t2, t3, t4, t5, t6, t7); \
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MOVOU (4*16)(RK), rk128; \
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MOVOU (4*16)(RK), rk128; \
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SM4_8BLOCKS_4ROUNDS(rk128, x, y, z, t0, t1, t2, t3, t4, t5, t6, t7); \
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SM4_8BLOCKS_4ROUNDS(rk128, x, y, z, t0, t1, t2, t3, t4, t5, t6, t7); \
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MOVOU (5*16)(RK), rk128; \
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MOVOU (5*16)(RK), rk128; \
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SM4_8BLOCKS_4ROUNDS(rk128, x, y, z, t0, t1, t2, t3, t4, t5, t6, t7); \
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SM4_8BLOCKS_4ROUNDS(rk128, x, y, z, t0, t1, t2, t3, t4, t5, t6, t7); \
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MOVOU (6*16)(RK), rk128; \
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MOVOU (6*16)(RK), rk128; \
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SM4_8BLOCKS_4ROUNDS(rk128, x, y, z, t0, t1, t2, t3, t4, t5, t6, t7); \
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SM4_8BLOCKS_4ROUNDS(rk128, x, y, z, t0, t1, t2, t3, t4, t5, t6, t7); \
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MOVOU (7*16)(RK), rk128; \
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MOVOU (7*16)(RK), rk128; \
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SM4_8BLOCKS_4ROUNDS(rk128, x, y, z, t0, t1, t2, t3, t4, t5, t6, t7); \
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SM4_8BLOCKS_4ROUNDS(rk128, x, y, z, t0, t1, t2, t3, t4, t5, t6, t7); \
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SSE_TRANSPOSE_MATRIX(t0, t1, t2, t3, x, y); \
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SSE_TRANSPOSE_MATRIX(t0, t1, t2, t3, x, y); \
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SSE_TRANSPOSE_MATRIX(t4, t5, t6, t7, x, y); \
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SSE_TRANSPOSE_MATRIX(t4, t5, t6, t7, x, y); \
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PSHUFB bswap_mask<>(SB), t3; \
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PSHUFB bswap_mask<>(SB), t3; \
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PSHUFB bswap_mask<>(SB), t2; \
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PSHUFB bswap_mask<>(SB), t2; \
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PSHUFB bswap_mask<>(SB), t1; \
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PSHUFB bswap_mask<>(SB), t1; \
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PSHUFB bswap_mask<>(SB), t0; \
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PSHUFB bswap_mask<>(SB), t0; \
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PSHUFB bswap_mask<>(SB), t7; \
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PSHUFB bswap_mask<>(SB), t7; \
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PSHUFB bswap_mask<>(SB), t6; \
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PSHUFB bswap_mask<>(SB), t6; \
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PSHUFB bswap_mask<>(SB), t5; \
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PSHUFB bswap_mask<>(SB), t5; \
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PSHUFB bswap_mask<>(SB), t4
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PSHUFB bswap_mask<>(SB), t4
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// SM4 sbox function, AVX version
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// SM4 sbox function, AVX version
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@ -366,7 +366,7 @@ GLOBL fk_mask<>(SB), 8, $16
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// - y: 128 bits temp register
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// - y: 128 bits temp register
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// - tmp: 128 bits temp register
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// - tmp: 128 bits temp register
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#define AVX_SM4_TAO_L1(x, y, tmp) \
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#define AVX_SM4_TAO_L1(x, y, tmp) \
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AVX_SM4_SBOX(x, y, tmp); \
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AVX_SM4_SBOX(x, y, tmp); \
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VPSHUFB r08_mask<>(SB), x, y; \ // y = x <<< 8
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VPSHUFB r08_mask<>(SB), x, y; \ // y = x <<< 8
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VPSHUFB r08_mask<>(SB), y, tmp; \ // tmp = x <<< 16
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VPSHUFB r08_mask<>(SB), y, tmp; \ // tmp = x <<< 16
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VPXOR x, y, y; \ // y = x ^ (x <<< 8)
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VPXOR x, y, y; \ // y = x ^ (x <<< 8)
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@ -408,7 +408,7 @@ GLOBL fk_mask<>(SB), 8, $16
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// - t3: 128 bits register for data
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// - t3: 128 bits register for data
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#define AVX_SM4_ROUND(index, RK, IND, x, y, tmp, t0, t1, t2, t3) \
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#define AVX_SM4_ROUND(index, RK, IND, x, y, tmp, t0, t1, t2, t3) \
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MOVL (index * 4)(RK)(IND*1), x; \
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MOVL (index * 4)(RK)(IND*1), x; \
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VPSHUFD $0, x, x; \
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VPSHUFD $0, x, x; \ // Use VBROADCASTSS ?
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VPXOR t1, x, x; \
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VPXOR t1, x, x; \
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VPXOR t2, x, x; \
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VPXOR t2, x, x; \
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VPXOR t3, x, x; \
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VPXOR t3, x, x; \
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@ -434,15 +434,15 @@ GLOBL fk_mask<>(SB), 8, $16
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SM4_ONE_ROUND_AVX(x, y, z, t3, t0, t1, t2); \
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SM4_ONE_ROUND_AVX(x, y, z, t3, t0, t1, t2); \
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#define AVX_SM4_4BLOCKS(RK, rk128, x, y, z, t0, t1, t2, t3) \
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#define AVX_SM4_4BLOCKS(RK, rk128, x, y, z, t0, t1, t2, t3) \
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VPSHUFB flip_mask<>(SB), t0, t0 \
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VPSHUFB flip_mask<>(SB), t0, t0 \
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VPSHUFB flip_mask<>(SB), t1, t1 \
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VPSHUFB flip_mask<>(SB), t1, t1 \
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VPSHUFB flip_mask<>(SB), t2, t2 \
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VPSHUFB flip_mask<>(SB), t2, t2 \
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VPSHUFB flip_mask<>(SB), t3, t3 \
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VPSHUFB flip_mask<>(SB), t3, t3 \
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; \
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; \
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AVX_SM4_4BLOCKS_WO_BS(RK, rk128, x, y, z, t0, t1, t2, t3)
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AVX_SM4_4BLOCKS_WO_BS(RK, rk128, x, y, z, t0, t1, t2, t3)
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#define AVX_SM4_4BLOCKS_WO_BS(RK, rk128, x, y, z, t0, t1, t2, t3) \
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#define AVX_SM4_4BLOCKS_WO_BS(RK, rk128, x, y, z, t0, t1, t2, t3) \
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TRANSPOSE_MATRIX(t0, t1, t2, t3, x, y) \
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TRANSPOSE_MATRIX(t0, t1, t2, t3, x, y) \
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VMOVDQU (0*16)(RK), rk128; \
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VMOVDQU (0*16)(RK), rk128; \
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SM4_4BLOCKS_4ROUNDS_AVX(rk128, x, y, z, t0, t1, t2, t3); \
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SM4_4BLOCKS_4ROUNDS_AVX(rk128, x, y, z, t0, t1, t2, t3); \
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VMOVDQU (1*16)(RK), rk128; \
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VMOVDQU (1*16)(RK), rk128; \
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@ -493,31 +493,31 @@ GLOBL fk_mask<>(SB), 8, $16
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VPSHUFB flip_mask<>(SB), t5, t5 \
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VPSHUFB flip_mask<>(SB), t5, t5 \
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VPSHUFB flip_mask<>(SB), t6, t6 \
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VPSHUFB flip_mask<>(SB), t6, t6 \
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VPSHUFB flip_mask<>(SB), t7, t7 \
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VPSHUFB flip_mask<>(SB), t7, t7 \
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; \
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; \
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AVX_SM4_8BLOCKS_WO_BS(RK, rk128, x, y, z, t0, t1, t2, t3, t4, t5, t6, t7)
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AVX_SM4_8BLOCKS_WO_BS(RK, rk128, x, y, z, t0, t1, t2, t3, t4, t5, t6, t7)
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#define AVX_SM4_8BLOCKS_WO_BS(RK, rk128, x, y, z, t0, t1, t2, t3, t4, t5, t6, t7) \
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#define AVX_SM4_8BLOCKS_WO_BS(RK, rk128, x, y, z, t0, t1, t2, t3, t4, t5, t6, t7) \
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TRANSPOSE_MATRIX(t0, t1, t2, t3, x, y) \
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TRANSPOSE_MATRIX(t0, t1, t2, t3, x, y) \
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TRANSPOSE_MATRIX(t4, t5, t6, t7, x, y) \
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TRANSPOSE_MATRIX(t4, t5, t6, t7, x, y) \
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VMOVDQU (0*16)(RK), rk128; \
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VMOVDQU (0*16)(RK), rk128; \
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SM4_8BLOCKS_4ROUNDS_AVX(rk128, x, y, z, t0, t1, t2, t3, t4, t5, t6, t7); \
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SM4_8BLOCKS_4ROUNDS_AVX(rk128, x, y, z, t0, t1, t2, t3, t4, t5, t6, t7); \
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VMOVDQU (1*16)(RK), rk128; \
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VMOVDQU (1*16)(RK), rk128; \
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SM4_8BLOCKS_4ROUNDS_AVX(rk128, x, y, z, t0, t1, t2, t3, t4, t5, t6, t7); \
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SM4_8BLOCKS_4ROUNDS_AVX(rk128, x, y, z, t0, t1, t2, t3, t4, t5, t6, t7); \
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VMOVDQU (2*16)(RK), rk128; \
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VMOVDQU (2*16)(RK), rk128; \
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SM4_8BLOCKS_4ROUNDS_AVX(rk128, x, y, z, t0, t1, t2, t3, t4, t5, t6, t7); \
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SM4_8BLOCKS_4ROUNDS_AVX(rk128, x, y, z, t0, t1, t2, t3, t4, t5, t6, t7); \
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VMOVDQU (3*16)(RK), rk128; \
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VMOVDQU (3*16)(RK), rk128; \
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SM4_8BLOCKS_4ROUNDS_AVX(rk128, x, y, z, t0, t1, t2, t3, t4, t5, t6, t7); \
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SM4_8BLOCKS_4ROUNDS_AVX(rk128, x, y, z, t0, t1, t2, t3, t4, t5, t6, t7); \
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VMOVDQU (4*16)(RK), rk128; \
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VMOVDQU (4*16)(RK), rk128; \
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SM4_8BLOCKS_4ROUNDS_AVX(rk128, x, y, z, t0, t1, t2, t3, t4, t5, t6, t7); \
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SM4_8BLOCKS_4ROUNDS_AVX(rk128, x, y, z, t0, t1, t2, t3, t4, t5, t6, t7); \
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VMOVDQU (5*16)(RK), rk128; \
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VMOVDQU (5*16)(RK), rk128; \
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SM4_8BLOCKS_4ROUNDS_AVX(rk128, x, y, z, t0, t1, t2, t3, t4, t5, t6, t7); \
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SM4_8BLOCKS_4ROUNDS_AVX(rk128, x, y, z, t0, t1, t2, t3, t4, t5, t6, t7); \
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VMOVDQU (6*16)(RK), rk128; \
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VMOVDQU (6*16)(RK), rk128; \
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SM4_8BLOCKS_4ROUNDS_AVX(rk128, x, y, z, t0, t1, t2, t3, t4, t5, t6, t7); \
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SM4_8BLOCKS_4ROUNDS_AVX(rk128, x, y, z, t0, t1, t2, t3, t4, t5, t6, t7); \
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VMOVDQU (7*16)(RK), rk128; \
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VMOVDQU (7*16)(RK), rk128; \
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SM4_8BLOCKS_4ROUNDS_AVX(rk128, x, y, z, t0, t1, t2, t3, t4, t5, t6, t7); \
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SM4_8BLOCKS_4ROUNDS_AVX(rk128, x, y, z, t0, t1, t2, t3, t4, t5, t6, t7); \
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; \ // Transpose matrix 4 x 4 32bits word
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; \ // Transpose matrix 4 x 4 32bits word
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TRANSPOSE_MATRIX(t0, t1, t2, t3, x, y) \
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TRANSPOSE_MATRIX(t0, t1, t2, t3, x, y) \
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TRANSPOSE_MATRIX(t4, t5, t6, t7, x, y) \
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TRANSPOSE_MATRIX(t4, t5, t6, t7, x, y) \
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VPSHUFB bswap_mask<>(SB), t0, t0 \
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VPSHUFB bswap_mask<>(SB), t0, t0 \
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VPSHUFB bswap_mask<>(SB), t1, t1 \
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VPSHUFB bswap_mask<>(SB), t1, t1 \
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VPSHUFB bswap_mask<>(SB), t2, t2 \
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VPSHUFB bswap_mask<>(SB), t2, t2 \
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@ -538,24 +538,24 @@ GLOBL fk_mask<>(SB), 8, $16
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// - yNibbleMask: 256 bits register stored nibble mask, should be loaded earlier.
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// - yNibbleMask: 256 bits register stored nibble mask, should be loaded earlier.
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#define AVX2_SM4_SBOX(x, y, z, xw, yw, xNibbleMask, yNibbleMask) \
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#define AVX2_SM4_SBOX(x, y, z, xw, yw, xNibbleMask, yNibbleMask) \
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VPAND yNibbleMask, x, z; \
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VPAND yNibbleMask, x, z; \
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VMOVDQU m1_low<>(SB), y; \
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VMOVDQU m1_low<>(SB), y; \
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VPSHUFB z, y, y; \
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VPSHUFB z, y, y; \
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VPSRLQ $4, x, x; \
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VPSRLQ $4, x, x; \
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VPAND yNibbleMask, x, x; \
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VPAND yNibbleMask, x, x; \
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VMOVDQU m1_high<>(SB), z; \
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VMOVDQU m1_high<>(SB), z; \
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VPSHUFB x, z, x; \
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VPSHUFB x, z, x; \
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VPXOR y, x, x; \
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VPXOR y, x, x; \
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VPSHUFB inverse_shift_rows<>(SB), x, x; \
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VPSHUFB inverse_shift_rows<>(SB), x, x; \
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VEXTRACTI128 $1, x, yw \
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VEXTRACTI128 $1, x, yw \
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VAESENCLAST xNibbleMask, xw, xw; \
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VAESENCLAST xNibbleMask, xw, xw; \
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VAESENCLAST xNibbleMask, yw, yw; \
|
VAESENCLAST xNibbleMask, yw, yw; \
|
||||||
VINSERTI128 $1, yw, x, x; \
|
VINSERTI128 $1, yw, x, x; \
|
||||||
VPANDN yNibbleMask, x, z; \
|
VPANDN yNibbleMask, x, z; \
|
||||||
VMOVDQU m2_low<>(SB), y; \
|
VMOVDQU m2_low<>(SB), y; \
|
||||||
VPSHUFB z, y, y; \
|
VPSHUFB z, y, y; \
|
||||||
VPSRLQ $4, x, x; \
|
VPSRLQ $4, x, x; \
|
||||||
VPAND yNibbleMask, x, x; \
|
VPAND yNibbleMask, x, x; \
|
||||||
VMOVDQU m2_high<>(SB), z; \
|
VMOVDQU m2_high<>(SB), z; \
|
||||||
VPSHUFB x, z, x; \
|
VPSHUFB x, z, x; \
|
||||||
VPXOR y, x, x
|
VPXOR y, x, x
|
||||||
|
|
||||||
@ -570,11 +570,11 @@ GLOBL fk_mask<>(SB), 8, $16
|
|||||||
// - yNibbleMask: 256 bits register stored nibble mask, should be loaded earlier.
|
// - yNibbleMask: 256 bits register stored nibble mask, should be loaded earlier.
|
||||||
#define AVX2_SM4_TAO_L1(x, y, z, xw, yw, xNibbleMask, yNibbleMask) \
|
#define AVX2_SM4_TAO_L1(x, y, z, xw, yw, xNibbleMask, yNibbleMask) \
|
||||||
AVX2_SM4_SBOX(x, y, z, xw, yw, xNibbleMask, yNibbleMask); \
|
AVX2_SM4_SBOX(x, y, z, xw, yw, xNibbleMask, yNibbleMask); \
|
||||||
VPSHUFB r08_mask<>(SB), x, y; \ // y = x <<< 8
|
VPSHUFB r08_mask<>(SB), x, y; \ // y = x <<< 8
|
||||||
VPSHUFB r08_mask<>(SB), y, z; \ // z = x <<< 16
|
VPSHUFB r08_mask<>(SB), y, z; \ // z = x <<< 16
|
||||||
VPXOR x, y, y; \ // y = x ^ (x <<< 8)
|
VPXOR x, y, y; \ // y = x ^ (x <<< 8)
|
||||||
VPXOR z, y, y; \ // y = x ^ (x <<< 8) ^ (x <<< 16)
|
VPXOR z, y, y; \ // y = x ^ (x <<< 8) ^ (x <<< 16)
|
||||||
VPSHUFB r08_mask<>(SB), z, z; \ // z = x <<< 24
|
VPSHUFB r08_mask<>(SB), z, z; \ // z = x <<< 24
|
||||||
VPXOR x, z, x; \ // x = x ^ (x <<< 24)
|
VPXOR x, z, x; \ // x = x ^ (x <<< 24)
|
||||||
VPSLLD $2, y, z; \
|
VPSLLD $2, y, z; \
|
||||||
VPSRLD $30, y, y; \
|
VPSRLD $30, y, y; \
|
||||||
@ -611,10 +611,10 @@ GLOBL fk_mask<>(SB), 8, $16
|
|||||||
// - t3: 256 bits register for data
|
// - t3: 256 bits register for data
|
||||||
#define AVX2_SM4_ROUND2(index, RK, x, y, xw, yw, tmp, t0, t1, t2, t3) \
|
#define AVX2_SM4_ROUND2(index, RK, x, y, xw, yw, tmp, t0, t1, t2, t3) \
|
||||||
VPBROADCASTD (index * 4)(RK), x; \
|
VPBROADCASTD (index * 4)(RK), x; \
|
||||||
VPXOR t1, x, x; \
|
VPXOR t1, x, x; \
|
||||||
VPXOR t2, x, x; \
|
VPXOR t2, x, x; \
|
||||||
VPXOR t3, x, x; \
|
VPXOR t3, x, x; \
|
||||||
AVX2_SM4_TAO_L1(x, y, tmp, xw, yw, X_NIBBLE_MASK, NIBBLE_MASK); \
|
AVX2_SM4_TAO_L1(x, y, tmp, xw, yw, X_NIBBLE_MASK, NIBBLE_MASK); \
|
||||||
VPXOR x, t0, t0
|
VPXOR x, t0, t0
|
||||||
|
|
||||||
// SM4 round function, AVX version, handle 128 bits
|
// SM4 round function, AVX version, handle 128 bits
|
||||||
@ -675,6 +675,8 @@ GLOBL fk_mask<>(SB), 8, $16
|
|||||||
// - index: round key index immediate number
|
// - index: round key index immediate number
|
||||||
// - x: 256 bits temp register, MUST use XDWORD!
|
// - x: 256 bits temp register, MUST use XDWORD!
|
||||||
// - y: 256 bits temp register, MUST use YDWORD!
|
// - y: 256 bits temp register, MUST use YDWORD!
|
||||||
|
// - tmp: 256 bits temp register
|
||||||
|
// - tmp1: 256 bits temp register
|
||||||
// - t0: 256 bits register for data as result
|
// - t0: 256 bits register for data as result
|
||||||
// - t1: 256 bits register for data
|
// - t1: 256 bits register for data
|
||||||
// - t2: 256 bits register for data
|
// - t2: 256 bits register for data
|
||||||
@ -694,16 +696,16 @@ GLOBL fk_mask<>(SB), 8, $16
|
|||||||
VPXOR x, t4, t4; \
|
VPXOR x, t4, t4; \
|
||||||
|
|
||||||
#define AVX2_SM4_16BLOCKS(RK, x, y, xw, yw, tmp, tmp1, t0, t1, t2, t3, t4, t5, t6, t7) \
|
#define AVX2_SM4_16BLOCKS(RK, x, y, xw, yw, tmp, tmp1, t0, t1, t2, t3, t4, t5, t6, t7) \
|
||||||
AVX2_SM4_16BLOCKS_ROUND(0, RK, x, y, xw, yw, tmp, tmp1, t0, t1, t2, t3, t4, t5, t6, t7); \
|
AVX2_SM4_16BLOCKS_ROUND(0, RK, x, y, xw, yw, tmp, tmp1, t0, t1, t2, t3, t4, t5, t6, t7); \
|
||||||
AVX2_SM4_16BLOCKS_ROUND(1, RK, x, y, xw, yw, tmp, tmp1, t1, t2, t3, t0, t5, t6, t7, t4); \
|
AVX2_SM4_16BLOCKS_ROUND(1, RK, x, y, xw, yw, tmp, tmp1, t1, t2, t3, t0, t5, t6, t7, t4); \
|
||||||
AVX2_SM4_16BLOCKS_ROUND(2, RK, x, y, xw, yw, tmp, tmp1, t2, t3, t0, t1, t6, t7, t4, t5); \
|
AVX2_SM4_16BLOCKS_ROUND(2, RK, x, y, xw, yw, tmp, tmp1, t2, t3, t0, t1, t6, t7, t4, t5); \
|
||||||
AVX2_SM4_16BLOCKS_ROUND(3, RK, x, y, xw, yw, tmp, tmp1, t3, t0, t1, t2, t7, t4, t5, t6); \
|
AVX2_SM4_16BLOCKS_ROUND(3, RK, x, y, xw, yw, tmp, tmp1, t3, t0, t1, t2, t7, t4, t5, t6); \
|
||||||
AVX2_SM4_16BLOCKS_ROUND(4, RK, x, y, xw, yw, tmp, tmp1, t0, t1, t2, t3, t4, t5, t6, t7); \
|
AVX2_SM4_16BLOCKS_ROUND(4, RK, x, y, xw, yw, tmp, tmp1, t0, t1, t2, t3, t4, t5, t6, t7); \
|
||||||
AVX2_SM4_16BLOCKS_ROUND(5, RK, x, y, xw, yw, tmp, tmp1, t1, t2, t3, t0, t5, t6, t7, t4); \
|
AVX2_SM4_16BLOCKS_ROUND(5, RK, x, y, xw, yw, tmp, tmp1, t1, t2, t3, t0, t5, t6, t7, t4); \
|
||||||
AVX2_SM4_16BLOCKS_ROUND(6, RK, x, y, xw, yw, tmp, tmp1, t2, t3, t0, t1, t6, t7, t4, t5); \
|
AVX2_SM4_16BLOCKS_ROUND(6, RK, x, y, xw, yw, tmp, tmp1, t2, t3, t0, t1, t6, t7, t4, t5); \
|
||||||
AVX2_SM4_16BLOCKS_ROUND(7, RK, x, y, xw, yw, tmp, tmp1, t3, t0, t1, t2, t7, t4, t5, t6); \
|
AVX2_SM4_16BLOCKS_ROUND(7, RK, x, y, xw, yw, tmp, tmp1, t3, t0, t1, t2, t7, t4, t5, t6); \
|
||||||
AVX2_SM4_16BLOCKS_ROUND(8, RK, x, y, xw, yw, tmp, tmp1, t0, t1, t2, t3, t4, t5, t6, t7); \
|
AVX2_SM4_16BLOCKS_ROUND(8, RK, x, y, xw, yw, tmp, tmp1, t0, t1, t2, t3, t4, t5, t6, t7); \
|
||||||
AVX2_SM4_16BLOCKS_ROUND(9, RK, x, y, xw, yw, tmp, tmp1, t1, t2, t3, t0, t5, t6, t7, t4); \
|
AVX2_SM4_16BLOCKS_ROUND(9, RK, x, y, xw, yw, tmp, tmp1, t1, t2, t3, t0, t5, t6, t7, t4); \
|
||||||
AVX2_SM4_16BLOCKS_ROUND(10, RK, x, y, xw, yw, tmp, tmp1, t2, t3, t0, t1, t6, t7, t4, t5); \
|
AVX2_SM4_16BLOCKS_ROUND(10, RK, x, y, xw, yw, tmp, tmp1, t2, t3, t0, t1, t6, t7, t4, t5); \
|
||||||
AVX2_SM4_16BLOCKS_ROUND(11, RK, x, y, xw, yw, tmp, tmp1, t3, t0, t1, t2, t7, t4, t5, t6); \
|
AVX2_SM4_16BLOCKS_ROUND(11, RK, x, y, xw, yw, tmp, tmp1, t3, t0, t1, t2, t7, t4, t5, t6); \
|
||||||
AVX2_SM4_16BLOCKS_ROUND(12, RK, x, y, xw, yw, tmp, tmp1, t0, t1, t2, t3, t4, t5, t6, t7); \
|
AVX2_SM4_16BLOCKS_ROUND(12, RK, x, y, xw, yw, tmp, tmp1, t0, t1, t2, t3, t4, t5, t6, t7); \
|
||||||
|
|||||||
@ -11,7 +11,6 @@
|
|||||||
#define t3 X5
|
#define t3 X5
|
||||||
|
|
||||||
#define XTMP6 X6
|
#define XTMP6 X6
|
||||||
#define IV X8
|
|
||||||
|
|
||||||
#include "aesni_macros_amd64.s"
|
#include "aesni_macros_amd64.s"
|
||||||
|
|
||||||
@ -27,15 +26,14 @@ TEXT ·encryptBlocksChain(SB),NOSPLIT,$0
|
|||||||
MOVQ src_len+40(FP), ptxLen
|
MOVQ src_len+40(FP), ptxLen
|
||||||
MOVQ iv+56(FP), SI
|
MOVQ iv+56(FP), SI
|
||||||
|
|
||||||
MOVUPS (SI), IV
|
MOVOU (SI), t0
|
||||||
|
|
||||||
loopSrc:
|
loopSrc:
|
||||||
CMPQ ptxLen, $16
|
CMPQ ptxLen, $16
|
||||||
JB done_sm4
|
JB done_sm4
|
||||||
SUBQ $16, ptxLen
|
SUBQ $16, ptxLen
|
||||||
|
|
||||||
MOVOU (ptx), t0
|
PXOR (ptx), t0
|
||||||
PXOR IV, t0
|
|
||||||
|
|
||||||
PSHUFB flip_mask<>(SB), t0
|
PSHUFB flip_mask<>(SB), t0
|
||||||
PSHUFD $1, t0, t1
|
PSHUFD $1, t0, t1
|
||||||
@ -60,7 +58,6 @@ loopRound:
|
|||||||
PALIGNR $4, t1, t0
|
PALIGNR $4, t1, t0
|
||||||
PSHUFB flip_mask<>(SB), t0
|
PSHUFB flip_mask<>(SB), t0
|
||||||
|
|
||||||
MOVOU t0, IV
|
|
||||||
MOVOU t0, (ctx)
|
MOVOU t0, (ctx)
|
||||||
|
|
||||||
LEAQ 16(ptx), ptx
|
LEAQ 16(ptx), ptx
|
||||||
@ -69,7 +66,7 @@ loopRound:
|
|||||||
JMP loopSrc
|
JMP loopSrc
|
||||||
|
|
||||||
done_sm4:
|
done_sm4:
|
||||||
MOVUPS IV, (SI)
|
MOVOU t0, (SI)
|
||||||
RET
|
RET
|
||||||
|
|
||||||
#undef ctx
|
#undef ctx
|
||||||
|
|||||||
Loading…
x
Reference in New Issue
Block a user