try order

This commit is contained in:
emmansun 2022-01-02 17:11:42 +08:00
parent ad7998eb85
commit 399db85ea8

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@ -142,8 +142,10 @@ TEXT ·precomputeTableAsm(SB),NOSPLIT,$0
VEOR B0.B16, B1.B16, B1.B16 VEOR B0.B16, B1.B16, B1.B16
ADD $14*16, pTbl ADD $14*16, pTbl
VREV64 B0.B16, B7.B16
VST1 [B7.B16, B1.B16], (pTbl) VREV64 B0.B16, B0.B16
VST1 [B0.B16, B1.B16], (pTbl)
VREV64 B0.B16, B0.B16
SUB $2*16, pTbl SUB $2*16, pTbl
VMOV B0.B16, B2.B16 VMOV B0.B16, B2.B16
@ -175,8 +177,9 @@ initLoop:
VEXT $8, B2.B16, B2.B16, B2.B16 VEXT $8, B2.B16, B2.B16, B2.B16
VEOR B2.B16, B3.B16, B3.B16 VEOR B2.B16, B3.B16, B3.B16
VREV64 B2.B16, B7.B16 VREV64 B2.B16, B2.B16
VST1 [B7.B16, B3.B16], (pTbl) VST1 [B2.B16, B3.B16], (pTbl)
VREV64 B2.B16, B2.B16
SUB $2*16, pTbl SUB $2*16, pTbl
BNE initLoop BNE initLoop