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https://github.com/emmansun/gmsm.git
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zuc: ppc64x genKeywordAsm 1
This commit is contained in:
Sun Yimin
GitHub
parent
7cfcabad54
commit
0904554637
20
zuc/core_ppc64x.go
Normal file
20
zuc/core_ppc64x.go
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// Copyright 2024 Sun Yimin. All rights reserved.
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// Use of this source code is governed by a MIT-style
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// license that can be found in the LICENSE file.
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//go:build (ppc64 || ppc64le) && !purego
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package zuc
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// Generate single keyword, 4 bytes.
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//
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//go:noescape
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func genKeywordAsm(s *zucState32) uint32
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// Generate multiple keywords, n*4 bytes.
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//
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//go:noescape
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func genKeyStreamAsm(keyStream []uint32, pState *zucState32)
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//go:noescape
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func genKeyStreamRev32Asm(keyStream []byte, pState *zucState32)
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294
zuc/core_ppc64x.s
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294
zuc/core_ppc64x.s
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@ -0,0 +1,294 @@
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// Copyright 2024 Sun Yimin. All rights reserved.
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// Use of this source code is governed by a MIT-style
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// license that can be found in the LICENSE file.
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//go:build (ppc64 || ppc64le) && !purego
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#include "textflag.h"
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DATA rcon<>+0x00(SB)/8, $0x0F0F0F0F0F0F0F0F // nibble mask
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DATA rcon<>+0x08(SB)/8, $0x0F0F0F0F0F0F0F0F
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DATA rcon<>+0x10(SB)/8, $0x691CA0D5B6C37F0A // affine transform matrix m1 low
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DATA rcon<>+0x18(SB)/8, $0x53269AEF8CF94530
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DATA rcon<>+0x20(SB)/8, $0x009837AF6CF45BC3 // affine transform matrix m1 high
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DATA rcon<>+0x28(SB)/8, $0xAB339C04C75FF068
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DATA rcon<>+0x30(SB)/8, $0x616EF1FE050A959A // affine transform matrix m2 low
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DATA rcon<>+0x38(SB)/8, $0xF5FA656A919E010E
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DATA rcon<>+0x40(SB)/8, $0x00A4E044CD692D89 // affine transform matrix m2 high
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DATA rcon<>+0x48(SB)/8, $0xA50145E168CC882C
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DATA rcon<>+0x50(SB)/8, $0x090F000E0F0F020A // P1
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DATA rcon<>+0x58(SB)/8, $0x0004000C07050309 // P1
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DATA rcon<>+0x60(SB)/8, $0x080D060507000C04 // P2
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DATA rcon<>+0x68(SB)/8, $0x0B010E0A0F030902 // P2
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DATA rcon<>+0x70(SB)/8, $0x02060A06000D0A0F // P3
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DATA rcon<>+0x78(SB)/8, $0x03030D0500090C0D // P3
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DATA rcon<>+0x70(SB)/8, $0x02060A06000D0A0F // P3
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DATA rcon<>+0x78(SB)/8, $0x03030D0500090C0D // P3
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DATA rcon<>+0x80(SB)/8, $0xff00ff00ff00ff00 // S0
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DATA rcon<>+0x88(SB)/8, $0xff00ff00ff00ff00
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DATA rcon<>+0x90(SB)/8, $0x00ff00ff00ff00ff // S1
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DATA rcon<>+0x98(SB)/8, $0x00ff00ff00ff00ff
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GLOBL rcon<>(SB), RODATA, $160
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#define M1L V20
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#define M1H V21
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#define M2L V22
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#define M2H V23
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#define V_FOUR V24
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#define NIBBLE_MASK V25
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#define S1_MASK V26
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#define S0_MASK V27
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#define P1 V28
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#define P2 V29
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#define P3 V30
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#define LOAD_CONSTS \
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VSPLTISW $4, V_FOUR \
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MOVD $rcon<>+0x00(SB), R4 \
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LXVD2X (R4)(R0), NIBBLE_MASK \
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MOVD $16, R5 \
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LXVD2X (R4)(R5), M1L \
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MOVD $32, R5 \
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LXVD2X (R4)(R5), M1H \
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MOVD $48, R5 \
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LXVD2X (R4)(R5), M2L \
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MOVD $64, R5 \
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LXVD2X (R4)(R5), M2H \
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MOVD $80, R5 \
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LXVD2X (R4)(R5), P1 \
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MOVD $96, R5 \
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LXVD2X (R4)(R5), P2 \
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MOVD $112, R5 \
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LXVD2X (R4)(R5), P3 \
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MOVD $128, R5 \
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LXVD2X (R4)(R5), S0_MASK \
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MOVD $144, R5 \
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LXVD2X (R4)(R5), S1_MASK
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#define S0_comput(IN_OUT, V_FOUR, XTMP1, XTMP2) \
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VSRW IN_OUT, V_FOUR, XTMP1; \
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VAND XTMP1, NIBBLE_MASK, XTMP1; \
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VAND IN_OUT, NIBBLE_MASK, IN_OUT; \
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VPERM P1, P1, IN_OUT, XTMP2; \
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VXOR XTMP1, XTMP2, XTMP2; \
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VPERM P2, P2, XTMP2, XTMP1; \
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VXOR IN_OUT, XTMP1, XTMP1; \
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VPERM P3, P3, XTMP1, IN_OUT; \
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VXOR XTMP2, IN_OUT, IN_OUT; \
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VSLW IN_OUT, V_FOUR, IN_OUT; \
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VXOR IN_OUT, XTMP1, IN_OUT; \
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VSPLTISB $5, XTMP1; \
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VRLB IN_OUT, XTMP1, IN_OUT
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// Affine Transform
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// parameters:
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// - L: table low nibbles
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// - H: table high nibbles
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// - x: 128 bits register as sbox input/output data
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// - y: 128 bits temp register
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// - z: 128 bits temp register
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#define AFFINE_TRANSFORM(L, H, V_FOUR, x, y, z) \
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VAND NIBBLE_MASK, x, z; \
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VPERM L, L, z, y; \
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VSRD x, V_FOUR, x; \
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VAND NIBBLE_MASK, x, z; \
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VPERM H, H, z, x; \
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VXOR y, x, x
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#define SHLDL(a, b, n) \ // NO SHLDL in GOLANG now
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SLW n, a, a \
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SRW n, b, b \
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OR b, a, a
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// zuc sbox function
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// parameters:
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// - x: 128 bits register as sbox input/output data
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// - y: 128 bits temp register
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// - z: 128 bits temp register
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#define S1_comput(x, y, z) \
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AFFINE_TRANSFORM(M1L, M1H, V_FOUR, x, y, z); \
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VSBOX x, x; \
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AFFINE_TRANSFORM(M2L, M2H, V_FOUR, x, y, z)
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#define OFFSET_FR1 (16*4)
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#define OFFSET_FR2 (17*4)
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#define OFFSET_BRC_X0 (18*4)
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#define OFFSET_BRC_X1 (19*4)
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#define OFFSET_BRC_X2 (20*4)
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#define OFFSET_BRC_X3 (21*4)
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#define F_R1 R7
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#define F_R2 R8
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#define BRC_X0 R9
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#define BRC_X1 R10
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#define BRC_X2 R11
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#define BRC_X3 R12
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#define BITS_REORG(idx, addr, tmpR1, tmpR2, tmpR3, tmpR4) \
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MOVWZ (((15 + idx) % 16)*4)(addr), BRC_X0 \
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MOVWZ (((14 + idx) % 16)*4)(addr), tmpR1 \
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MOVWZ (((11 + idx) % 16)*4)(addr), BRC_X1 \
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MOVWZ (((9 + idx) % 16)*4)(addr), tmpR2 \
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MOVWZ (((7 + idx) % 16)*4)(addr), BRC_X2 \
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MOVWZ (((5 + idx) % 16)*4)(addr), tmpR3 \
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MOVWZ (((2 + idx) % 16)*4)(addr), BRC_X4 \
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MOVWZ (((0 + idx) % 16)*4)(addr), tmpR4 \
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SRW $15, BRC_X0, BRC_X0 \
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SLW $16, tmpR1, tmpR1 \
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SLW $1, tmpR2, tmpR2 \
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SLW $1, tmpR3, tmpR3 \
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SLW $1, tmpR4, tmpR4 \
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SHLDL(BRC_X0, tmpR1, $16) \
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SHLDL(BRC_X1, tmpR2, $16) \
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SHLDL(BRC_X2, tmpR3, $16) \
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SHLDL(BRC_X4, tmpR4, $16)
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#define LOAD_STATE(addr) \
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MOVWZ OFFSET_FR1(addr), F_R1 \
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MOVWZ OFFSET_FR2(addr), F_R2 \
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MOVWZ OFFSET_BRC_X0(addr), BRC_X0 \
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MOVWZ OFFSET_BRC_X1(addr), BRC_X1 \
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MOVWZ OFFSET_BRC_X2(addr), BRC_X2 \
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MOVWZ OFFSET_BRC_X3(addr), BRC_X3
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#define SAVE_STATE(addr) \
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MOVW F_R1, OFFSET_FR1(addr) \
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MOVW F_R2, OFFSET_FR2(addr) \
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MOVW BRC_X0, OFFSET_BRC_X0(addr) \
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MOVW BRC_X1, OFFSET_BRC_X1(addr) \
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MOVW BRC_X2, OFFSET_BRC_X2(addr) \
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MOVW BRC_X3, OFFSET_BRC_X3(addr)
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#define NONLIN_FUN(AX, BX, CX, DX) \
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XOR F_R1, BRC_X0, AX \ // F_R1 xor BRC_X0
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ADD F_R2, AX \ // W = (F_R1 xor BRC_X1) + F_R2
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ADD BRC_X1, F_R1 \ // W1= F_R1 + BRC_X1
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XOR BRC_X2, F_R2 \ // W2= F_R2 ^ BRC_X2
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\
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SLW $16, F_R1, DX \
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SRW $16, F_R2, CX \
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OR CX, DX \ // P = (W1 << 16) | (W2 >> 16)
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SHLDL(F_R2, F_R1, $16) \ // Q = (W2 << 16) | (W1 >> 16)
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ROTLW $2, DX, BX \ // start L1
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ROTLW $24, DX, CX \
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XOR CX, DX \
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XOR BX, DX \
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ROTLW $8, BX \
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XOR BX, DX \
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ROTLW $8, BX \
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XOR BX, DX, BX \ // U = L1(P) = EDX, hi(RDX)=0
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RLDICL $0, BX, $32, DX \ // make sure hi(RDX)=0
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ROTLW $8, F_R2, BX \
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ROTLW $14, F_R2, CX \
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XOR BX, F_R2 \
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XOR CX, F_R2 \
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ROTLW $8, CX \
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XOR CX, F_R2 \
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ROTLW $8, CX \
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XOR CX, F_R2 \ // V = L2(Q) = R11D, hi(R11)=0
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SLD $32, F_R2 \ // DX = V || U
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XOR F_R2, DX \
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MTVSRD DX, V0 \ // save V || U to V0
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S0_comput(V0, V_FOUR, V1, V2) \
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S1_comput(V0, V1, V2) \
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VAND S1_MASK, V0, V0 \
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VAND S0_MASK, V1, V1 \
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VXOR V0, V1, V0 \
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MFVSRD V0, DX \
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SRD $32, DX, F_R1 \
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MOVWZ DX, F_R2
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#define LFSR_UPDT(idx, addr, W, tmpR1, tmpR2, tmpR3, tmpR4 ) \
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MOVWZ (((0 + idx) % 16)*4)(addr), tmpR1 \
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MOVWZ (((4 + idx) % 16)*4)(addr), tmpR2 \
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MOVWZ (((10 + idx) % 16)*4)(addr), tmpR3 \
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MOVWZ (((13 + idx) % 16)*4)(addr), tmpR4 \
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\ // Calculate 64-bit LFSR feedback
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ADD tmpR1, W \
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SLD $8, tmpR1 \
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SLD $20, tmpR2 \
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SLD $21, tmpR3 \
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SLD $17, tmpR4 \
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ADD tmpR1, W \
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ADD tmpR2, W \
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ADD tmpR3, W \
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ADD tmpR4, W \
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MOVWZ (((15 + idx) % 16)*4)(addr), tmpR4 \
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SLD $15, tmpR4 \
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ADD tmpR4, W \
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\ // Reduce it to 31-bit value
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SRD $31, W, tmpR1 \
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AND $0x7FFFFFFF, W \
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ADD tmpR1, W \
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\
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SRD $31, W, tmpR1 \
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AND $0x7FFFFFFF, W \
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ADD tmpR1, W \
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\ // LFSR_S16 = (LFSR_S15++) = W
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MOVW W, (((0 + idx) % 16)*4)(addr)
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#define RESTORE_LFSR_0(addr, tmpR1, tmpR2, tmpR3, tmpR4) \
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MOVWZ (addr), tmpR1 \
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MOVD $4, tmpR4 \
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LXVD2X (tmpR4)(addr), V0 \
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MOVD $20, tmpR4 \
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LXVD2X (tmpR4)(addr), V1 \
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MOVD $36, tmpR4 \
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LXVD2X (tmpR4)(addr), V2 \
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MOVD 52(addr), tmpR2 \
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MOVWZ 60(addr), tmpR3 \
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STXVD2X V0, (addr) \
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MOVD $16, tmpR4 \
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STXVD2X V1, (tmpR4)(addr) \
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MOVD $32, tmpR4 \
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STXVD2X V2, (tmpR4)(addr) \
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MOVD tmpR2, 48(addr) \
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MOVW tmpR3, 56(addr) \
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MOVW tmpR1, 60(addr)
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#define RESTORE_LFSR_2(addr, tmpR1, tmpR2, tmpR3) \
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MOVD (addr), tmpR1 \
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MOVD 8(addr), tmpR2 \
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LXVD2X (tmpR2)(addr), V0 \
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MOVD 24(addr), tmpR2 \
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LXVD2X (tmpR2)(addr), V1 \
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MOVD 40(addr), tmpR2 \
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LXVD2X (tmpR2)(addr), V2 \
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MOVD 56(addr), tmpR3 \
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\
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STXVD2X V0, (addr) \
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MOVD 16(addr), tmpR2 \
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STXVD2X V1, (tmpR2)(addr) \
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MOVD 32(addr), tmpR2 \
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STXVD2X V2, (tmpR2)(addr) \
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MOVW tmpR3, 48(addr) \
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MOVW tmpR1, 56(addr)
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// func genKeywordAsm(s *zucState32) uint32
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TEXT ·genKeywordAsm(SB),NOSPLIT,$0
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LOAD_CONSTS
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MOVQ pState+0(FP), R4
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LOAD_STATE(R4)
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NONLIN_FUN(R14, R15, R16, R17)
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// (BRC_X3 xor W) as result
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XOR BRC_X3, R14
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MOVW R14, ret+8(FP)
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// LFSRWithWorkMode
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XOR R14, R14
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LFSR_UPDT(0, R4, R14, R15, R16, R17, R18)
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SAVE_STATE(R4)
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RESTORE_LFSR_0(R4, R15, R16, R17, R18)
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RET
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// func genKeyStreamAsm(keyStream []uint32, pState *zucState32)
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TEXT ·genKeyStreamAsm(SB),NOSPLIT,$0
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RET
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// func genKeyStreamRev32Asm(keyStream []byte, pState *zucState32)
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TEXT ·genKeyStreamRev32Asm(SB),NOSPLIT,$0
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RET
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21
zuc/core_ppc64x_test.go
Normal file
21
zuc/core_ppc64x_test.go
Normal file
@ -0,0 +1,21 @@
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// Copyright 2024 Sun Yimin. All rights reserved.
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// Use of this source code is governed by a MIT-style
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// license that can be found in the LICENSE file.
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//go:build (ppc64 || ppc64le) && !purego
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package zuc
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import "testing"
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func Test_genKeywordAsm_case1(t *testing.T) {
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s, _ := newZUCState([]byte{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, []byte{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0})
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z1 := genKeywordAsm(s)
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if z1 != 0x27bede74 {
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t.Errorf("expected=%x, result=%x\n", 0x27bede74, z1)
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}
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z2 := genKeywordAsm(s)
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if z2 != 0x018082da {
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t.Errorf("expected=%x, result=%x\n", 0x018082da, z2)
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}
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}
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