2024-09-12 15:53:53 +08:00
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#define LOAD_CONSTS(baseAddrReg, offsetReg) \
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LXVD2X (baseAddrReg)(R0), M0; \
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MOVD $0x10, offsetReg; \
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LXVD2X (baseAddrReg)(offsetReg), M1; \
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MOVD $0x20, offsetReg; \
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LXVD2X (baseAddrReg)(offsetReg), M2; \
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MOVD $0x30, offsetReg; \
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LXVD2X (baseAddrReg)(offsetReg), M3; \
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MOVD $0x40, offsetReg; \
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LXVD2X (baseAddrReg)(offsetReg), REVERSE_WORDS; \
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MOVD $0x50, offsetReg; \
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LXVD2X (baseAddrReg)(offsetReg), NIBBLE_MASK; \
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MOVD $0x70, offsetReg; \
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LXVD2X (baseAddrReg)(offsetReg), M1L; \
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MOVD $0x80, offsetReg; \
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LXVD2X (baseAddrReg)(offsetReg), M1H; \
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MOVD $0x90, offsetReg; \
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LXVD2X (baseAddrReg)(offsetReg), M2L; \
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MOVD $0xa0, offsetReg; \
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LXVD2X (baseAddrReg)(offsetReg), M2H
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#ifdef GOARCH_ppc64le
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#define NEEDS_PERMW
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#define PPC64X_LXVW4X(RA,RB,VT) \
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LXVW4X (RA+RB), VT \
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VPERM VT, VT, ESPERMW, VT
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#define PPC64X_STXVW4X(VS, RA, RB) \
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VPERM VS, VS, ESPERMW, VS \
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STXVW4X VS, (RA+RB)
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#else
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#define PPC64X_LXVW4X(RA,RB,VT) LXVW4X (RA+RB), VT
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#define PPC64X_STXVW4X(VS, RA, RB) STXVW4X VS, (RA+RB)
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#endif // defined(GOARCH_ppc64le)
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// r = s <<< n
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// Due to VSPLTISW's limitation, the n MUST be [0, 15],
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// If n > 15, we have to call it multiple times.
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// VSPLTISW takes a 5-bit immediate value as an operand.
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// I also did NOT find one vector instruction to use immediate value for ROTL.
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#define PROLD(s, r, tmp, n) \
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VSPLTISW $n, tmp \
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VRLW s, tmp, r
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// input: from high to low
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// t0 = t0.S3, t0.S2, t0.S1, t0.S0
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// t1 = t1.S3, t1.S2, t1.S1, t1.S0
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// t2 = t2.S3, t2.S2, t2.S1, t2.S0
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// t3 = t3.S3, t3.S2, t3.S1, t3.S0
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// output: from high to low
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// t0 = t3.S0, t2.S0, t1.S0, t0.S0
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// t1 = t3.S1, t2.S1, t1.S1, t0.S1
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// t2 = t3.S2, t2.S2, t1.S2, t0.S2
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// t3 = t3.S3, t2.S3, t1.S3, t0.S3
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#define PRE_TRANSPOSE_MATRIX(T0, T1, T2, T3) \
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VPERM T0, T1, M0, TMP0; \
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VPERM T2, T3, M0, TMP1; \
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VPERM T0, T1, M1, TMP2; \
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VPERM T2, T3, M1, TMP3; \
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VPERM TMP0, TMP1, M2, T0; \
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VPERM TMP0, TMP1, M3, T1; \
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VPERM TMP2, TMP3, M2, T2; \
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VPERM TMP2, TMP3, M3, T3
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// input: from high to low
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// t0 = t0.S3, t0.S2, t0.S1, t0.S0
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// t1 = t1.S3, t1.S2, t1.S1, t1.S0
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// t2 = t2.S3, t2.S2, t2.S1, t2.S0
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// t3 = t3.S3, t3.S2, t3.S1, t3.S0
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// output: from high to low
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// t0 = t0.S0, t1.S0, t2.S0, t3.S0
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// t1 = t0.S1, t1.S1, t2.S1, t3.S1
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// t2 = t0.S2, t1.S2, t2.S2, t3.S2
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// t3 = t0.S3, t1.S3, t2.S3, t3.S3
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#define TRANSPOSE_MATRIX(T0, T1, T2, T3) \
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VPERM T1, T0, M0, TMP0; \
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VPERM T1, T0, M1, TMP1; \
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VPERM T3, T2, M0, TMP2; \
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VPERM T3, T2, M1, TMP3; \
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VPERM TMP2, TMP0, M2, T0; \
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VPERM TMP2, TMP0, M3, T1; \
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VPERM TMP3, TMP1, M2, T2; \
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VPERM TMP3, TMP1, M3, T3; \
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// Affine Transform
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// parameters:
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// - L: table low nibbles
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// - H: table high nibbles
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// - x: 128 bits register as sbox input/output data
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// - y: 128 bits temp register
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// - z: 128 bits temp register
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#define AFFINE_TRANSFORM(L, H, V_FOUR, x, y, z) \
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VAND NIBBLE_MASK, x, z; \
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VPERM L, L, z, y; \
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VSRD x, V_FOUR, x; \
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VAND NIBBLE_MASK, x, z; \
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VPERM H, H, z, x; \
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VXOR y, x, x
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// Affine Transform
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// parameters:
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// - L: table low nibbles
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// - H: table high nibbles
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// - x: 128 bits register as sbox input/output data
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// - y: 128 bits temp register
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// - z: 128 bits temp register
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#define AFFINE_TRANSFORM_NOTX(L, H, V_FOUR, x, y, z) \
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VNOR x, x, z; \ // z = NOT(x)
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VAND NIBBLE_MASK, z, z; \
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VPERM L, L, z, y; \
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VSRD x, V_FOUR, x; \
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VAND NIBBLE_MASK, x, z; \
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VPERM H, H, z, x; \
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VXOR y, x, x
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// SM4 sbox function
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// parameters:
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// - x: 128 bits register as sbox input/output data
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// - y: 128 bits temp register
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// - z: 128 bits temp register
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#define SM4_SBOX(x, y, z) \
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AFFINE_TRANSFORM(M1L, M1H, V_FOUR, x, y, z); \
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2024-09-23 14:10:37 +08:00
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VSBOX x, x; \
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AFFINE_TRANSFORM(M2L, M2H, V_FOUR, x, y, z)
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2024-09-12 15:53:53 +08:00
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// SM4 TAO L1 function
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// parameters:
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// - x: 128 bits register as TAO_L1 input/output data
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// - tmp1: 128 bits temp register
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// - tmp2: 128 bits temp register
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// - tmp3: 128 bits temp register
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#define SM4_TAO_L1(x, tmp1, tmp2, tmp3) \
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SM4_SBOX(x, tmp1, tmp2); \
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; \ //#################### 4 parallel L1 linear transforms ##################//
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VSPLTISW $8, tmp3; \
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VRLW x, tmp3, tmp1; \ // tmp1 = x <<< 8
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VRLW tmp1, tmp3, tmp2; \ // tmp2 = x <<< 16
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VXOR x, tmp1, tmp1; \ // tmp1 = x xor (x <<< 8)
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VXOR tmp1, tmp2, tmp1; \ // tmp1 = x xor (x <<< 8) xor (x <<< 16)
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VRLW tmp2, tmp3, tmp2; \ // tmp2 = x <<< 24
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VXOR tmp2, x, x; \ // x = x xor (x <<< 24)
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VSPLTISW $2, tmp3; \
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VRLW tmp1, tmp3, tmp1; \ // tmp1 = (x xor (x <<< 8) xor (x <<< 16)) <<< 2
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VXOR tmp1, x, x
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// SM4 round function
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// t0 ^= tao_l1(t1^t2^t3^xk)
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// parameters:
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// - RK: round key register
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// - x: 128 bits temp register
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// - tmp1: 128 bits temp register
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// - tmp2: 128 bits temp register
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// - tmp3: 128 bits temp register
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// - t0: 128 bits register for data as result
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// - t1: 128 bits register for data
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// - t2: 128 bits register for data
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// - t3: 128 bits register for data
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#define SM4_ROUND(RK, x, tmp1, tmp2, tmp3, t0, t1, t2, t3) \
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VXOR RK, t1, x; \
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VXOR t2, x, x; \
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VXOR t3, x, x; \
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SM4_TAO_L1(x, tmp1, tmp2, tmp3); \
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VXOR x, t0, t0
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#define PROCESS_8BLOCKS_4ROUND \
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VSPLTW $0, V8, V9; \
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SM4_ROUND(V9, TMP0, TMP1, TMP2, TMP3, V0, V1, V2, V3); \
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SM4_ROUND(V9, TMP0, TMP1, TMP2, TMP3, V4, V5, V6, V7); \
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VSPLTW $1, V8, V9; \
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SM4_ROUND(V9, TMP0, TMP1, TMP2, TMP3, V1, V2, V3, V0); \
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SM4_ROUND(V9, TMP0, TMP1, TMP2, TMP3, V5, V6, V7, V4); \
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VSPLTW $2, V8, V9; \
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SM4_ROUND(V9, TMP0, TMP1, TMP2, TMP3, V2, V3, V0, V1); \
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SM4_ROUND(V9, TMP0, TMP1, TMP2, TMP3, V6, V7, V4, V5); \
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VSPLTW $3, V8, V9; \
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SM4_ROUND(V9, TMP0, TMP1, TMP2, TMP3, V3, V0, V1, V2); \
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SM4_ROUND(V9, TMP0, TMP1, TMP2, TMP3, V7, V4, V5, V6)
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#define PROCESS_4BLOCKS_4ROUND \
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VSPLTW $0, V8, V9; \
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SM4_ROUND(V9, TMP0, TMP1, TMP2, TMP3, V0, V1, V2, V3); \
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VSPLTW $1, V8, V9; \
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SM4_ROUND(V9, TMP0, TMP1, TMP2, TMP3, V1, V2, V3, V0); \
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VSPLTW $2, V8, V9; \
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SM4_ROUND(V9, TMP0, TMP1, TMP2, TMP3, V2, V3, V0, V1); \
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VSPLTW $3, V8, V9; \
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SM4_ROUND(V9, TMP0, TMP1, TMP2, TMP3, V3, V0, V1, V2)
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#define PROCESS_SINGLEBLOCK_4ROUND \
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SM4_ROUND(V8, TMP0, TMP1, TMP2, TMP3, V0, V1, V2, V3); \
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VSLDOI $4, V8, V8, V8; \
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SM4_ROUND(V8, TMP0, TMP1, TMP2, TMP3, V1, V2, V3, V0); \
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VSLDOI $4, V8, V8, V8; \
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SM4_ROUND(V8, TMP0, TMP1, TMP2, TMP3, V2, V3, V0, V1); \
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VSLDOI $4, V8, V8, V8; \
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SM4_ROUND(V8, TMP0, TMP1, TMP2, TMP3, V3, V0, V1, V2)
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