2024-08-02 13:02:25 +08:00
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#define mul2Inline \
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VMOV TW.D[1], I; \
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ASR $63, I; \
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VMOV I, K0.D2; \
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VAND POLY.B16, K0.B16, K0.B16; \
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\
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VUSHR $63, TW.D2, K1.D2; \
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VEXT $8, K1.B16, ZERO.B16, K1.B16; \
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VSHL $1, TW.D2, TW.D2; \
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VEOR K0.B16, TW.B16, TW.B16; \
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VEOR K1.B16, TW.B16, TW.B16
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#define mul2GBInline \
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VREV64 TW.B16, TW.B16; \
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VEXT $8, TW.B16, TW.B16, TW.B16; \
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\
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VMOV TW.D[0], I; \
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LSL $63, I; \
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ASR $63, I; \
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VMOV I, K0.D2; \
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VAND POLY.B16, K0.B16, K0.B16; \
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\
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VSHL $63, TW.D2, K1.D2; \
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VEXT $8, ZERO.B16, K1.B16, K1.B16; \
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VUSHR $1, TW.D2, TW.D2; \
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VEOR K0.B16, TW.B16, TW.B16; \
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VEOR K1.B16, TW.B16, TW.B16; \
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\
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VEXT $8, TW.B16, TW.B16, TW.B16; \
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VREV64 TW.B16, TW.B16
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#define prepare4Tweaks \
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VMOV TW.B16, T0.B16; \
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mul2Inline; \
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VMOV TW.B16, T1.B16; \
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mul2Inline; \
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VMOV TW.B16, T2.B16; \
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mul2Inline; \
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VMOV TW.B16, T3.B16; \
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mul2Inline
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#define prepare8Tweaks \
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prepare4Tweaks; \
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VMOV TW.B16, T4.B16; \
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mul2Inline; \
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VMOV TW.B16, T5.B16; \
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mul2Inline; \
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VMOV TW.B16, T6.B16; \
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mul2Inline; \
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VMOV TW.B16, T7.B16; \
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mul2Inline
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#define prepareGB4Tweaks \
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VMOV TW.B16, T0.B16; \
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mul2GBInline; \
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VMOV TW.B16, T1.B16; \
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mul2GBInline; \
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VMOV TW.B16, T2.B16; \
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mul2GBInline; \
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VMOV TW.B16, T3.B16; \
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mul2GBInline
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#define prepareGB8Tweaks \
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prepareGB4Tweaks; \
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VMOV TW.B16, T4.B16; \
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mul2GBInline; \
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VMOV TW.B16, T5.B16; \
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mul2GBInline; \
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VMOV TW.B16, T6.B16; \
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mul2GBInline; \
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VMOV TW.B16, T7.B16; \
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mul2GBInline
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