2023-08-21 10:22:46 +08:00
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//go:build arm64 && !purego
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// +build arm64,!purego
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#include "textflag.h"
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#define B0 V0
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#define T1 V1
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#define T2 V2
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#define POLY V3
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#define ZERO V4
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2023-08-21 10:25:45 +08:00
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#define TW R0
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2023-08-21 10:22:46 +08:00
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#define GB R1
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#define I R2
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// func mul2(tweak *[blockSize]byte, isGB bool)
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TEXT ·mul2(SB),NOSPLIT,$0
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2023-08-21 10:25:45 +08:00
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MOVD tweak+0(FP), TW
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2023-08-21 10:22:46 +08:00
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MOVB isGB+8(FP), GB
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2023-08-21 10:25:45 +08:00
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VLD1 (TW), [B0.B16]
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2023-08-21 10:22:46 +08:00
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VEOR POLY.B16, POLY.B16, POLY.B16
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VEOR ZERO.B16, ZERO.B16, ZERO.B16
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CMP $1, GB
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BEQ gb_alg
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MOVD $0x87, I
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VMOV I, POLY.D[0]
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VMOV B0.D[1], I
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ASR $63, I
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VMOV I, T1.D[0]
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VMOV I, T1.D[1]
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VAND POLY.B16, T1.B16, T1.B16
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VUSHR $63, B0.D2, T2.D2
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VEXT $8, T2.B16, ZERO.B16, T2.B16
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VSHL $1, B0.D2, B0.D2
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VEOR T1.B16, B0.B16, B0.B16
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VEOR T2.B16, B0.B16, B0.B16
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2023-08-21 10:25:45 +08:00
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VST1 [B0.B16], (TW)
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2023-08-21 10:22:46 +08:00
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RET
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gb_alg:
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MOVD $0xE1, I
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LSL $56, I
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VMOV I, POLY.D[1]
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VREV64 B0.B16, B0.B16
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VEXT $8, B0.B16, B0.B16, B0.B16
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VMOV B0.D[0], I
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LSL $63, I
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ASR $63, I
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VMOV I, T1.D[0]
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VMOV I, T1.D[1]
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VAND POLY.B16, T1.B16, T1.B16
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VSHL $63, B0.D2, T2.D2
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VEXT $8, ZERO.B16, T2.B16, T2.B16
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VUSHR $1, B0.D2, B0.D2
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VEOR T1.B16, B0.B16, B0.B16
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VEOR T2.B16, B0.B16, B0.B16
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VEXT $8, B0.B16, B0.B16, B0.B16
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VREV64 B0.B16, B0.B16
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2023-08-21 10:25:45 +08:00
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VST1 [B0.B16], (TW)
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2023-08-21 10:22:46 +08:00
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RET
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// func doubleTweaks(tweak *[blockSize]byte, tweaks []byte, isGB bool)
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TEXT ·doubleTweaks(SB),NOSPLIT,$0
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2023-08-21 10:25:45 +08:00
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MOVD tweak+0(FP), TW
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2023-08-21 10:22:46 +08:00
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MOVD tweaks+8(FP), R3
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MOVD tweaks_len+16(FP), R4
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MOVB isGB+32(FP), GB
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LSR $4, R4
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EOR R5, R5
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VEOR POLY.B16, POLY.B16, POLY.B16
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VEOR ZERO.B16, ZERO.B16, ZERO.B16
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2023-08-21 10:25:45 +08:00
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VLD1 (TW), [B0.B16]
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2023-08-21 10:22:46 +08:00
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CMP $1, GB
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BEQ dt_gb_alg
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MOVD $0x87, I
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VMOV I, POLY.D[0]
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loop:
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VST1.P [B0.B16], 16(R3)
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VMOV B0.D[1], I
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ASR $63, I
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VMOV I, T1.D[0]
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VMOV I, T1.D[1]
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VAND POLY.B16, T1.B16, T1.B16
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VUSHR $63, B0.D2, T2.D2
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VEXT $8, T2.B16, ZERO.B16, T2.B16
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VSHL $1, B0.D2, B0.D2
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VEOR T1.B16, B0.B16, B0.B16
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VEOR T2.B16, B0.B16, B0.B16
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ADD $1, R5
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CMP R4, R5
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BNE loop
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2023-08-21 10:25:45 +08:00
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VST1 [B0.B16], (TW)
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2023-08-21 10:22:46 +08:00
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RET
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dt_gb_alg:
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MOVD $0xE1, I
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LSL $56, I
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VMOV I, POLY.D[1]
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gb_loop:
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VST1.P [B0.B16], 16(R3)
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VREV64 B0.B16, B0.B16
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VEXT $8, B0.B16, B0.B16, B0.B16
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VMOV B0.D[0], I
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LSL $63, I
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ASR $63, I
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VMOV I, T1.D[0]
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VMOV I, T1.D[1]
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VAND POLY.B16, T1.B16, T1.B16
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VSHL $63, B0.D2, T2.D2
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VEXT $8, ZERO.B16, T2.B16, T2.B16
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VUSHR $1, B0.D2, B0.D2
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VEOR T1.B16, B0.B16, B0.B16
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VEOR T2.B16, B0.B16, B0.B16
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VEXT $8, B0.B16, B0.B16, B0.B16
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VREV64 B0.B16, B0.B16
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ADD $1, R5
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CMP R4, R5
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BNE gb_loop
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2023-08-21 10:25:45 +08:00
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VST1 [B0.B16], (TW)
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2023-08-21 10:22:46 +08:00
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RET
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